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/*** Copyright 2006, Ira W. Snyder (devel@irasnyder.com)* License: GNU General Public License v2 (or, at your option, any later* version)*//*** Name: Ira Snyder* Class: CS365 - Computer Architecture* Project #1 - Part 2* Due: 2006-02-06*//*** File: MUL4_test.v* Purpose: Test module for the MUL4 module.*/module MUL4_test;reg[0:3] a, b;wire[0:7] w_out;MUL4 mult (a, b, w_out);initial begin$monitor ("time=%0d a=%b b=%b prod=%b", $time, a, b, w_out);endinitial begina = 'b0010; b = 'b1011;#10 a = 'b1010; b = 'b0101;#10 a = 'b1100; b = 'b0011;#10 a = 'b1001; b = 'b0110;#10 $finish;endendmodule