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/**
 * Copyright 2006, Ira W. Snyder (devel@irasnyder.com)
 * License: GNU General Public License v2 (or, at your option, any later
 * version)
 */

/**
 * Name: Ira Snyder
 * Class: CS365 - Computer Architecture
 * Project #1 - Part 2
 * Due: 2006-02-06
 */

/**
 * File: MUL4_test.v
 * Purpose: Test module for the MUL4 module.
 */

module MUL4_test;

    reg[0:3] a, b;
    wire[0:7] w_out;

    MUL4 mult (a, b, w_out);

    initial begin
        $monitor ("time=%0d a=%b b=%b prod=%b", $time, a, b, w_out);
    end

    initial begin
            a = 'b0011; b = 'b0011;
        #10 a = 'b0001; b = 'b1100;
        #10 a = 'b1100; b = 'b0011;
        #10 a = 'b0101; b = 'b1010;
        #10 $finish;
    end

endmodule