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/**
 * Copyright 2006, Ira W. Snyder (devel@irasnyder.com)
 * License: GNU General Public License v2 (or, at your option, any later
 * version)
 */

/**
 * Name: Ira Snyder
 * Class: CS365 - Computer Architecture
 * Project #1 - Part 1
 * Due: 2006-02-06
 */

/**
 * File: ALU4_test.v
 * Purpose: Test the ALU4 module.
 */

module ALU4_test;

    reg[0:3] a, b;
    reg[0:1] op;
    reg cin;
    wire[0:3] result;
    wire cout;

    ALU4 alu (a, b, cin, op, cout, result);
    initial begin
        $monitor ("time=%0d a=%b b=%b op=%b cin=%b cout=%b result=%b",
            $time, a, b, op, cin, cout, result);
    end

    initial begin
        $display ("Required Values\n");
           a='b0101; b='b1011; op='b00; cin=0;
        #1 a='b0101; b='b1011; op='b01;
        #1 a='b0101; b='b1011; op='b10;
        #1 a='b1101; b='b0011; op='b00;
        #1 a='b1010; b='b0011; op='b01;
        #1 a='b0101; b='b0011; op='b10;
        #1 a='b1010; b='b1001; op='b10;

        #1 $display ("\n\nMy Own Values\n");
        #1 a='b0000; b='b0000; cin=0; op='b00; $display; $display("AND");
        #1 a='b0001; b='b0000; cin=0; op='b00;
        #1 a='b0101; b='b1010; cin=0; op='b00;
        #1 a='b1100; b='b1111; cin=0; op='b00;
        #1 a='b1010; b='b1010; cin=0; op='b00;

        #1 a='b0000; b='b0000; cin=0; op='b01; $display; $display ("OR");
        #1 a='b0001; b='b0000; cin=0; op='b01;
        #1 a='b0101; b='b1010; cin=0; op='b01;
        #1 a='b1100; b='b1111; cin=0; op='b01;
        #1 a='b1010; b='b1010; cin=0; op='b01;

        #1 a='b0000; b='b0000; cin=0; op='b10; $display; $display ("ADD");
        #1 a='b0001; b='b0000; cin=0; op='b10;
        #1 a='b0001; b='b0000; cin=1; op='b10;
        #1 a='b0001; b='b0001; cin=0; op='b10;
        #1 a='b0001; b='b0001; cin=1; op='b10;
        #1 a='b0011; b='b1100; cin=0; op='b10;
        #1 a='b0011; b='b1100; cin=1; op='b10;

        #1 a='b0000; b='b0000; cin=0; op='b11; $display; $display ("SUB");
        #1 a='b0001; b='b0001; cin=0; op='b11;
        #1 a='b0001; b='b0001; cin=1; op='b11;
        #1 a='b0011; b='b0001; cin=0; op='b11;
        #1 a='b0011; b='b0001; cin=1; op='b11;
        #1 a='b1001; b='b0001; cin=0; op='b11;
        #1 a='b1001; b='b0001; cin=1; op='b11;
    end

endmodule