Subversion Repositories programming

module ALU4 (a, b, cin, op, cout, result);
    input[0:3] a, b;
    input[0:1] op;
    input cin;

    output[0:3] result;
    output cout;

    wire bit3_cout, bit2_cout, bit1_cout;

    ALU1 bit3 (a[3], b[3], cin, op, bit3_cout, result[3]);
    ALU1 bit2 (a[2], b[2], bit3_cout, op, bit2_cout, result[2]);
    ALU1 bit1 (a[1], b[1], bit2_cout, op, bit1_cout, result[1]);
    ALU1 bit0 (a[0], b[0], bit1_cout, op, cout, result[0]);
endmodule

module test_ALU4;
    reg[0:3] x;
    reg[0:3] y;
    reg[0:1] op;
    reg cin;

    wire[0:3] result;
    wire cout;

    initial begin
        $monitor ("time=%0d a=%b b=%b op=%b cin=%b cout=%b result=%b",
                $time, x, y, op, cin, cout, result);
    end

    initial begin

           x='b0000; y='b0000; op='b00; cin=0; $display ("\nAND");
        #1 x='b0001; y='b0000; op='b00; cin=0;
        #1 x='b0010; y='b0000; op='b00; cin=0;
        #1 x='b0011; y='b0000; op='b00; cin=0;
        #1 x='b0011; y='b1100; op='b00; cin=0;
        #1 x='b1010; y='b0101; op='b00; cin=0;
        #1 x='b1010; y='b1010; op='b00; cin=0;
        #1 x='b0101; y='b0101; op='b00; cin=0;
        
        #1 x='b0001; y='b0000; op='b01; cin=0; $display ("\nOR");
        #1 x='b1001; y='b0110; op='b01; cin=0;

        #1 x='b0001; y='b0001; op='b10; cin=0; $display ("\nADD");
        #1 x='b0011; y='b0011; op='b10; cin=0;

        #1 x='b0011; y='b0001; op='b11; cin=0; $display ("\nSUB");
    end

    ALU4 alu4 (x, y, cin, op, cout, result);
    
endmodule