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/**
 * Copyright 2006, Ira W. Snyder (devel@irasnyder.com)
 * License: GNU General Public License v2 (or, at your option, any later
 * version)
 */

/**
 * Name: Ira Snyder
 * Class: CS365 - Computer Architecture
 * Project #1 - Part 1 (support)
 * Due: 2006-02-06
 */

/**
 * File: ALU1_test.v
 * Purpose: Test module for the ALU1 module.
 */

module ALU1_test;

    reg a, b, cin;
    reg[0:1] op;
    wire cout, result;

    ALU1 alu1 (a, b, cin, op, cout, result);

    initial begin
        $monitor ("time=%0d a=%b b=%b op=%b cin=%b cout=%b result=%b",
            $time, a, b, op, cin, cout, result);
    end

    initial begin
           a=0; b=0; cin=0; op=00; $display; $display("AND");
        #1 a=0; b=0; cin=1; op=00;
        #1 a=0; b=1; cin=0; op=00;
        #1 a=0; b=1; cin=1; op=00;
        #1 a=1; b=0; cin=0; op=00;
        #1 a=1; b=0; cin=1; op=00;
        #1 a=1; b=1; cin=0; op=00;
        #1 a=1; b=1; cin=1; op=00;

        #1 a=0; b=0; cin=0; op=01; $display; $display ("OR");
        #1 a=0; b=0; cin=1; op=01;
        #1 a=0; b=1; cin=0; op=01;
        #1 a=0; b=1; cin=1; op=01;
        #1 a=1; b=0; cin=0; op=01;
        #1 a=1; b=0; cin=1; op=01;
        #1 a=1; b=1; cin=0; op=01;
        #1 a=1; b=1; cin=1; op=01;

        #1 a=0; b=0; cin=0; op=10; $display; $display ("ADD");
        #1 a=0; b=0; cin=1; op=10;
        #1 a=0; b=1; cin=0; op=10;
        #1 a=0; b=1; cin=1; op=10;
        #1 a=1; b=0; cin=0; op=10;
        #1 a=1; b=0; cin=1; op=10;
        #1 a=1; b=1; cin=0; op=10;
        #1 a=1; b=1; cin=1; op=10;

        #1 a=0; b=0; cin=0; op=11; $display; $display ("SUB");
        #1 a=0; b=0; cin=1; op=11;
        #1 a=0; b=1; cin=0; op=11;
        #1 a=0; b=1; cin=1; op=11;
        #1 a=1; b=0; cin=0; op=11;
        #1 a=1; b=0; cin=1; op=11;
        #1 a=1; b=1; cin=0; op=11;
        #1 a=1; b=1; cin=1; op=11;
    end

endmodule