Subversion Repositories programming

//Basic unit: 2-input and gate
module AND_2 (in1, in2, out);
   input in1, in2;
   output out;
   assign out = in1 & in2;
endmodule

//Basic unit: 2-input or gate
module OR_2 (in1, in2, out);
   input in1, in2;
   output out;
   assign out = in1 || in2;
endmodule

//Basic unit: 3-input or gate
module OR_3(in1, in2, in3, out);
   input in1, in2, in3;
   output out;
   assign out = in1 || in2 || in3;
endmodule

//Basic unit: 3-input and gate
module AND_3 (in1, in2, in3, out);
   input in1, in2, in3;
   output out;
   assign out = in1 & in2 & in3;
endmodule

//Basic unit: 4-input or gate
module OR_4 (in1, in2, in3, in4, out);
   input in1, in2, in3, in4;
   output out;
   assign out = in1 || in2 || in3 || in4;
endmodule

//Basic unit: Invert
module NOT_1 (in, out);
   input in;
   output out;
   assign out = ~in;
endmodule

//Basic unit: module for a 2x1 multiplexer
module Mux2 (a, b, op, out);
   input a, b, op;
   output out;
   wire w1, w2, w3;

   NOT_1 not1 (op, w1);

   AND_2 and2 (a, w1, w2);
   AND_2 and1 (b, op, w3);

   OR_2 or1 (w2, w3, out);
endmodule

//basic unit: 3-input NAND gate
module NAND_3 (in1, in2, in3, out);
  input in1, in2, in3;
  output out;
  assign out = ~(in1 & in2 & in3);
endmodule

//basic unit: 4-input NAND gate
module NAND_4 (in1, in2, in3, in4, out);
  input in1, in2, in3, in4;
  output out;
  assign out = ~(in1 & in2 & in3 & in4);
endmodule

// basic unit: 2-input NAND gate
module NAND_2 (in1, in2, out);
   input in1, in2;
   output out;
   assign out = ~(in1 & in2);
endmodule

// basic unit: 2-input NOR gate
module NOR_2 ( in1, in2, out);
   input in1, in2;
   output out;
   assign out = ~(in1 || in2);
endmodule

// module for a 4x1 multiplexer
module Mux4 (a, b, c, d, op, out);
   input a, b, c, d;
   input [0:1]op;
   output out;
   wire w1, w2, f1, f2, f3, f4;

   //instantiate two NOT gates
   NOT_1 not1 (op[0:0], w1);
   NOT_1 not2 (op[1:1], w2);

   //instantiate four 3-input NAND gates
   NAND_3 nand3_1 (a, w1, w2, f1);
   NAND_3 nand3_2 (b, w1, op[1:1], f2);
   NAND_3 nand3_3 (c, op[0:0], w2, f3);
   NAND_3 nand3_4 (d, op[0:0], op[1:1], f4);

   //instantiate one 4-input NAND gate
   NAND_4 nand4_1 (f1, f2, f3, f4, out);
endmodule

// CarryOut module for the 1-bit Adder
//cout = cin . a + cin . b + a . b
module CarryOut (carryIn, a, b, carryOut);
   input carryIn, a, b;
   output carryOut;

   wire w1, w2, w3;

   AND_2  and1 (carryIn, a, w1);
   AND_2  and2 (carryIn, b, w2);
   AND_2  and3 (a, b, w3);

   OR_3   or1 (w1, w2, w3, carryOut);
endmodule

//Sum module for 1-bit ALU
module Sum (carryIn, a, b, sum);
   input a, b, carryIn;
   wire w1, w2, w3, f1, f2, f3, f4;
   output sum;

   NOT_1 not1 (carryIn, w1);
   NOT_1 not2 (a, w2);
   NOT_1 not3 (b, w3);

   AND_3 and1 (a, w3, w1, f1);
   AND_3 and2 (w2, b, w1, f2);
   AND_3 and3 (w2, w3, carryIn, f3);
   AND_3 and4 (a, b, carryIn, f4);

   OR_4 or1 (f1, f2, f3, f4, sum);

endmodule

//module a 1-bit adder
module OneBitAdder (carryIn, a, b, carryOut, sum);
   input carryIn, a, b;
   output carryOut, sum;

   Sum sum_gate (carryIn, a, b, sum);
   CarryOut cout (carryIn, a, b, carryOut);
endmodule


// module for the 1-bit ALU
module ALU1 (a, b, binvert, carryIn, op, carryOut, result);
   input a, b, binvert, carryIn;
   input [0:1]op;
   output carryOut, result;
   wire w1, w2, w3, w4, w5, w6;
   wire dead;

   AND_2 and1 (a, w2, w3);
   OR_2 or1 (a, w2, w4);

   NOT_1 not1 (b, w1);
   Mux2 mux2 (b, w1, binvert, w2);

   OneBitAdder adder (carryIn, a, w2, carryOut, w5);

   Mux4 mux4 (w3, w4, w5, dead, op, result);
endmodule

module test_alu1;

    reg a, b, cin, binvert;
    reg[0:1] op;
    wire cout, result;

    ALU1 alu1 (a, b, binvert, cin, op, cout, result);

    initial begin
        $monitor ("time=%0d a=%b b=%b op=%b cin=%b cout=%b result=%b",
            $time, a, b, op, cin, cout, result);
    end

    initial begin
        binvert=0;
           a=0; b=0; cin=0; op=00; $display; $display("AND");
        #1 a=0; b=0; cin=1; op=00;
        #1 a=0; b=1; cin=0; op=00;
        #1 a=0; b=1; cin=1; op=00;
        #1 a=1; b=0; cin=0; op=00;
        #1 a=1; b=0; cin=1; op=00;
        #1 a=1; b=1; cin=0; op=00;
        #1 a=1; b=1; cin=1; op=00;

        #1 a=0; b=0; cin=0; op=01; $display; $display ("OR");
        #1 a=0; b=0; cin=1; op=01;
        #1 a=0; b=1; cin=0; op=01;
        #1 a=0; b=1; cin=1; op=01;
        #1 a=1; b=0; cin=0; op=01;
        #1 a=1; b=0; cin=1; op=01;
        #1 a=1; b=1; cin=0; op=01;
        #1 a=1; b=1; cin=1; op=01;

        #1 a=0; b=0; cin=0; op='b10; $display; $display ("ADD");
        #1 a=0; b=0; cin=1; op='b10;
        #1 a=0; b=1; cin=0; op='b10;
        #1 a=0; b=1; cin=1; op='b10;
        #1 a=1; b=0; cin=0; op='b10;
        #1 a=1; b=0; cin=1; op='b10;
        #1 a=1; b=1; cin=0; op='b10;
        #1 a=1; b=1; cin=1; op='b10; // <-- BUG HERE

        binvert=1;
        #1 a=0; b=0; cin=0; op='b10; $display; $display ("SUB");
        #1 a=0; b=0; cin=1; op='b10;
        #1 a=0; b=1; cin=0; op='b10;
        #1 a=0; b=1; cin=1; op='b10;
        #1 a=1; b=0; cin=0; op='b10;
        #1 a=1; b=0; cin=1; op='b10;
        #1 a=1; b=1; cin=0; op='b10;
        #1 a=1; b=1; cin=1; op='b10;
    end

endmodule