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Line 29... Line 29...
29 
    input clk;
 29 
    input clk;
30 
 
 30 
 
31 
    reg[0:3] value;
 31 
    reg[0:3] value;
32 
 
 32 
 
33 
    always @(in) begin
 33 
    always @(in) begin
34 
        $display ("multiplicand changed");
 - 
 
35 
        value = in;
 34 
        value = in;
36 
    end
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    end
37 
 
 36 
 
38 
    assign out = value;
 37 
    assign out = value;
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 38 
 
Line 48... Line 47...
48 
    reg[0:7] value;
 47 
    reg[0:7] value;
49 
 
 48 
 
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    always @(right4) begin
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    always @(right4) begin
51 
        value[0:3] = 'b0000;
 50 
        value[0:3] = 'b0000;
52 
        value[4:7] = right4;
 51 
        value[4:7] = right4;
53 
        $display ("right4 changed");
 - 
 
54 
    end
 52 
    end
55 
 
 53 
 
56 
    always @(negedge clk) begin
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    always @(negedge clk) begin
57 
        if (shift_op == 1) begin
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        if (shift_op == 1) begin
58 
            if (write_op == 1) begin
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            if (write_op == 1) begin
59 
                $display ("write");
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                value[0:3] = left4[0:3];
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                value[0:3] = left4[0:3];
61 
            end
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            end
62
59
63 
            $display ("shift");
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            value = value >> 1;
 60 
            value = value >> 1;
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        end
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        end
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    end
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    end
67 
 
 63 
 
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    assign out = value;
 64 
    assign out = value;
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 65 
 
70 
endmodule
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endmodule
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 67 
 
72 
module testme;
 68 
module testme;
73 
 
 69 
 
74 
    /*
 - 
 
75 
    reg[0:3] a, b;
 70 
    reg[0:3] a, b;
76 
    wire[0:7] prod;
 - 
 
77 
 
 - 
 
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    initial begin
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79 
        $monitor ("time=%0d a=%b b=%b prod=%b", $time, a, b, prod);
 - 
 
80 
    end
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81 
 
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82 
    initial begin
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83 
           a = 'b0000; b = 'b0000;
 - 
 
84 
        #4 a = 'b0011; b = 'b1111;
 - 
 
85 
        #4
 - 
 
86 
        $finish;
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87 
    end
 - 
 
88 
 
 - 
 
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    MUL4 m4 (a, b, prod);
 - 
 
90 
    */
 - 
 
91 
 
 - 
 
92 
    /*
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93 
    wire[0:1] aop;
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    wire wop, sop;
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    reg clk;
 - 
 
96 
    reg pin;
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97 
 
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    always begin
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99 
        #1 clk = ~clk;
 - 
 
100 
    end
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101 
 
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102 
    initial begin
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103 
        pin = 'b0; clk='b0;
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104 
        #1 pin = 'b1;
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105 
        #1 pin = 'b0;
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106 
        #1 pin = 'b1;
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107 
        #1 pin = 'b1;
 - 
 
108 
        #1 pin = 'b0;
 - 
 
109 
        #1
 - 
 
110 
        $finish;
 - 
 
111 
    end
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112 
 
 - 
 
113 
    initial begin
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114 
        $monitor ("time=%0d pin=%b aop=%b wop=%b sop=%b clk=%b", $time, pin, aop, wop, sop, clk);
 - 
 
115 
    end
 - 
 
116 
 
 - 
 
117 
    MUL4_CONTROL mc (pin, aop, wop, sop, clk);
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118 
    */
 - 
 
119 
 
 - 
 
120 
    /*
 - 
 
121 
    reg[0:3] l, r;
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122 
    wire sop, wop;
 - 
 
123 
    wire[0:1] aop;
 - 
 
124 
    wire[0:7] prod;
 71 
    wire[0:7] w_out;
125 
    reg clk;
 - 
 
126 
 
 - 
 
127 
    always begin
 - 
 
128 
        #1 clk = ~clk;
 - 
 
129 
    end
 - 
 
130 
 
 72 
 
131 
    initial begin
 - 
 
132 
        clk = 'b0;
 - 
 
133 
        #1 l = 'b1000; r='b1111;
 73 
    MUL4 mult (a, b, w_out);
134 
        #1
 - 
 
135 
        #1
 - 
 
136 
        #1
 - 
 
137 
        #1
 - 
 
138 
        #1
 - 
 
139 
        #1
 - 
 
140 
        #1
 - 
 
141 
        #1
 - 
 
142 
        #1
 - 
 
143 
        #1
 - 
 
144 
        #1
 - 
 
145 
        #1
 - 
 
146 
        #1
 - 
 
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        #1
 - 
 
148 
        $finish;
 - 
 
149 
    end
 - 
 
150 
 
 74 
 
151 
    initial begin
 75 
    initial begin
152 
        $monitor ("time=%0d prod=%b aop=%b wop=%b sop=%b clk=%b l=%b r=%b",
 76 
        $monitor ("time=%0d a=%b b=%b prod=%b", $time, a, b, w_out);
153 
                $time, prod, aop, wop, sop, clk, l, r);
 - 
 
154 
    end
 77 
    end
155 
 
 - 
 
156 
    MUL4_CONTROL mc (prod[7], aop, wop, sop, clk);
 - 
 
157 
    MUL4_PRODUCT mp (l, r, sop, wop, prod, clk);
 - 
 
158 
    */
 78
159 
 
 - 
 
160 
    reg[0:3] a, b;
 - 
 
161 
    wire[0:7] w_out;
 - 
 
162 
 
 - 
 
163 
    MUL4_2 mult (a, b, w_out);
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164 
 
 - 
 
165 
    initial begin
 79 
    initial begin
166 
           a = 'b0011; b = 'b0011;
 80 
            a = 'b0011; b = 'b0011;
167 
        #10 a = 'b0001; b = 'b1100;
 81 
        #10 a = 'b0001; b = 'b1100;
168 
        #10 a = 'b1100; b = 'b0011;
 82 
        #10 a = 'b1100; b = 'b0011;
169 
        #10 a = 'b0101; b = 'b1010;
 83 
        #10 a = 'b0101; b = 'b1010;
170 
        #8
 84 
        #8
171 
        #2 $finish;
 85 
        #2 $finish;
172 
    end
 86 
    end
173 
 
 87 
 
174 
endmodule
 88 
endmodule
175 
 
 89 
 
176 
module MUL4_2 (a, b, out);
 90 
module MUL4 (a, b, out);
177 
 
 91 
 
178 
    input[0:3] a, b;
 92 
    input[0:3] a, b;
179 
    output[0:7] out;
 93 
    output[0:7] out;
180 
 
 94 
 
181 
    reg[0:3] counter;
 95 
    reg[0:3] counter;
Line 192... Line 106...
192 
    end
 106 
    end
193 
 
 107 
 
194 
    always @(negedge clk) begin
 108 
    always @(negedge clk) begin
195 
        counter = counter + 'b1;
 109 
        counter = counter + 'b1;
196 
    end
 110 
    end
197 
 
 111 
/*
198 
    initial begin
 112 
    initial begin
199 
        $monitor ("time=%0d counter=%b clk=%b w_mout=%b w_prod=%b w_aop=%b w_sop=%b w_wop=%b out=%b",
 113 
        $monitor ("time=%0d counter=%b clk=%b w_mout=%b w_prod=%b w_aop=%b w_sop=%b w_wop=%b out=%b",
200 
               $time, counter, clk, w_mout, w_prod, w_aop, w_sop, w_wop, out);
 114 
               $time, counter, clk, w_mout, w_prod, w_aop, w_sop, w_wop, out);
201 
    end
 115 
    end
202 
 
 - 
 
203 
    always @(negedge clk) begin
 - 
 
204 
        $display ("negedge clk");
 - 
 
205 
    end
 - 
 
206 
 
 116 
*/
207 
    wire[0:7] w_prod;
 117 
    wire[0:7] w_prod;
208 
    wire[0:3] w_mout, w_alu_out;
 118 
    wire[0:3] w_mout, w_alu_out;
209 
    wire[0:1] w_aop;
 119 
    wire[0:1] w_aop;
210 
    wire w_sop, w_wop, w_cout;
 120 
    wire w_sop, w_wop, w_cout;
211 
    reg cin;
 121 
    reg cin;