WebSVN – programming – Diff – /school/cs365/p1/MUL4.v

 /* A 4-bit multiplier, following the algorithm from
  * Pg. 179, Figure 3.7. */
-module MUL4 (mul1, mul2, result, clk);
-    input[0:3] mul1, mul2;
-    output[0:7] result;
-    input clk;
-    wire[0:3] w_alu_out;
-    wire[0:3] w_multiplicand;
-    wire[0:7] w_product;
-    wire[0:1] w_alu_op;
-    wire w_write_op, w_shift_op;
-    reg[0:3] count;
-    MUL4_MULTIPLICAND m_mcand (mul1, w_multiplicand, clk);
-    MUL4_PRODUCT m_prod (w_alu_out, mul2, w_shift_op, w_write_op, w_product, clk);
-    MUL4_CONTROL m_ctrl (w_product[7], w_alu_op, w_write_op, w_shift_op, clk);
-    ALU4 m_alu (w_product[0:3], w_multiplicand, cin, w_alu_op, cout, w_alu_out);
-    always @(mul1 or mul2) begin
-        count = 'b0000;
-    end
-    always @(clk) begin
-        if (count == 4) begin
-            $display ("set the result");
-            force result = w_product;
-        end
-        count = count + 1;
-    end
-endmodule
-module MUL4_2 (mul1, mul2, out);
-    input[0:3] mul1, mul2;
-    output[0:7] out;
-    initial begin
-        clk = 'b0;
-    end
-    always begin
-        clk = ~clk;
-    end
-endmodule
-module MUL4_CONTROL (prod_in, alu_op, write_op, shift_op, clk);
+module MUL4_CONTROL (prod_in, alu_op, write_op, shift_op, clk, ctr);
     input prod_in, clk;
+    input[0:3] ctr;
     output[0:1] alu_op;
     output write_op, shift_op;
+    always @(negedge clk) begin
+        if (ctr <= 4) begin
+            force write_op = prod_in;
-    reg[0:1] a_op;
+            force shift_op = 'b1;
-    reg w_op, s_op;
+            force alu_op = 'b10;
-    initial begin
+        end else begin
+            release write_op;
-        a_op = 'b00;
+            release shift_op;
-        w_op = 'b0;
+            release alu_op;
-        s_op = 'b0;
+        end
     end
-    always @(clk) begin
-        if (prod_in == 'b1)
-            begin
-                a_op = 'b10; // ADD
-                w_op = 'b1;  // STORE
-                s_op = 'b1;  // SHIFT
-            end
-        else
-            begin
-                a_op = 'b00; // AND, unnecessary
-                w_op = 'b0;  // DO NOT WRITE
-                s_op = 'b1;  // SHIFT
-            end
-    end //always
-    assign alu_op = a_op;
-    assign write_op = w_op;
-    assign shift_op = s_op;
 endmodule
 module MUL4_MULTIPLICAND (in, out, clk);
     input[0:3] in;
         value[0:3] = 'b0000;
         value[4:7] = right4;
         $display ("right4 changed");
     end
-    always @(clk) begin
+    always @(negedge clk) begin
-        $display ("value=%b", value);
         if (shift_op == 1) begin
-            $display ("shift 1");
             if (write_op == 1) begin
-                $display ("write 1");
+                $display ("write");
                 value[0:3] = left4[0:3];
             end
+            $display ("shift");
             value = value >> 1;
         end
     end
     assign out = value;
 endmodule
 module testme;
+    /*
     reg[0:3] a, b;
     wire[0:7] prod;
     initial begin
         $monitor ("time=%0d a=%b b=%b prod=%b", $time, a, b, prod);
     end
     initial begin
-           clk = 'b0;
            a = 'b0000; b = 'b0000;
         #4 a = 'b0011; b = 'b1111;
         #4
         $finish;
     end
+    MUL4 m4 (a, b, prod);
+    */
+    /*
+    wire[0:1] aop;
+    wire wop, sop;
+    reg clk;
+    reg pin;
+    always begin
+        #1 clk = ~clk;
+    end
+    initial begin
+        pin = 'b0; clk='b0;
+        #1 pin = 'b1;
+        #1 pin = 'b0;
+        #1 pin = 'b1;
+        #1 pin = 'b1;
+        #1 pin = 'b0;
+        #1
+        $finish;
+    end
+    initial begin
+        $monitor ("time=%0d pin=%b aop=%b wop=%b sop=%b clk=%b", $time, pin, aop, wop, sop, clk);
+    end
+    MUL4_CONTROL mc (pin, aop, wop, sop, clk);
+    */
+    /*
+    reg[0:3] l, r;
+    wire sop, wop;
+    wire[0:1] aop;
+    wire[0:7] prod;
+    reg clk;
+    always begin
+        #1 clk = ~clk;
+    end
+    initial begin
+        clk = 'b0;
+        #1 l = 'b1000; r='b1111;
+        #1
+        #1
+        #1
+        #1
+        #1
+        #1
+        #1
+        #1
+        #1
+        #1
+        #1
+        #1
+        #1
+        #1
+        $finish;
+    end
+    initial begin
+        $monitor ("time=%0d prod=%b aop=%b wop=%b sop=%b clk=%b l=%b r=%b",
+                $time, prod, aop, wop, sop, clk, l, r);
+    end
+    MUL4_CONTROL mc (prod[7], aop, wop, sop, clk);
+    MUL4_PRODUCT mp (l, r, sop, wop, prod, clk);
+    */
+    reg[0:3] a, b;
+    wire[0:7] w_out;
+    MUL4_2 mult (a, b, w_out);
+    initial begin
+           a = 'b0011; b = 'b0011;
+        #10 a = 'b0001; b = 'b1100;
+        #10 a = 'b1100; b = 'b0011;
+        #10 a = 'b0101; b = 'b1010;
+        #8
+        #2 $finish;
+    end
+endmodule
+module MUL4_2 (a, b, out);
+    input[0:3] a, b;
+    output[0:7] out;
+    reg[0:3] counter;
     reg clk;
+    initial begin
-    // Clock Generator
+        clk = 'b0;
+        counter ='b0000;
+        cin = 'b0;
+    end
     always begin
         #1 clk = ~clk;
     end
+    always @(negedge clk) begin
+        counter = counter + 'b1;
+    end
+    initial begin
+        $monitor ("time=%0d counter=%b clk=%b w_mout=%b w_prod=%b w_aop=%b w_sop=%b w_wop=%b out=%b",
+               $time, counter, clk, w_mout, w_prod, w_aop, w_sop, w_wop, out);
+    end
+    always @(negedge clk) begin
+        $display ("negedge clk");
+    end
+    wire[0:7] w_prod;
+    wire[0:3] w_mout, w_alu_out;
+    wire[0:1] w_aop;
+    wire w_sop, w_wop, w_cout;
+    reg cin;
+    MUL4_PRODUCT mp (w_alu_out, a, w_sop, w_wop, w_prod, clk);
-    MUL4 m4 (a, b, prod, clk);
+    MUL4_MULTIPLICAND mm (b, w_mout, clk);
+    MUL4_CONTROL mc (w_prod[7], w_aop, w_wop, w_sop, clk, counter);
+    ALU4 ma (w_prod[0:3], w_mout, cin, w_aop, w_cout, w_alu_out);
+    always @(counter) begin
+        if (counter == 4) begin
+            force out = w_prod;
+            counter = 'b1111; //reset counter
+        end else begin
+            release out;
+        end
+    end
 endmodule

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