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/**
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 * Copyright 2006, Ira W. Snyder (devel@irasnyder.com)
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 * License: GNU General Public License v2 (or, at your option, any later
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 * version)
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 */
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/**
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 * Name: Ira Snyder
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 * Class: CS365 - Computer Architecture
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 * Project #1 - Part 2
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 * Due: 2006-02-06
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 */
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/**
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 * File: MUL4.v
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 * Purpose: Implementation of a 4-bit multiplier.
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 *
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/* A 4-bit multiplier, following the algorithm from
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 * A 4-bit multiplier, following the algorithm from
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 * Pg. 179, Figure 3.7 of the book Computer Organization and Design by
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 * Pg. 179, Figure 3.7. */
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 * Patterson and Hennessey.
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 */
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// This controls the multiplication unit.
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module MUL4_CONTROL (prod_in, alu_op, write_op, shift_op, clk, ctr);
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module MUL4_CONTROL (prod_in, alu_op, write_op, shift_op, clk, ctr);
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    input prod_in, clk;
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    input prod_in, clk;
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    input[0:3] ctr;
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    input[0:3] ctr;
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    output[0:1] alu_op;
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    output[0:1] alu_op;
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    output write_op, shift_op;
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    output write_op, shift_op;
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    // Only trigger at the negative edge of the clock. We should stay constant
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    // in all other cases.
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    always @(negedge clk) begin
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    always @(negedge clk) begin
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        // If we have a "low enough" counter, set the correct
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        // operations based on the input of the last bit in the product
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        // register.
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        //
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        // If the counter is out of range, then don't do anything, since we
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        // want to give the hardware some time to accept new values, for the
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        // next multiplication operation.
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        if (ctr <= 4) begin
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        if (ctr <= 4) begin
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            force write_op = prod_in;
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            force write_op = prod_in;
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            force shift_op = 'b1;
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            force shift_op = 'b1;
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            force alu_op = 'b10;
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            force alu_op = 'b10;
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        end else begin
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        end else begin
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        end
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        end
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    end
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    end
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endmodule
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endmodule
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// This stores the "right" mutiplying number until it changes.
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module MUL4_MULTIPLICAND (in, out, clk);
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module MUL4_MULTIPLICAND (in, out, clk);
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    input[0:3] in;
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    input[0:3] in;
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    output[0:3] out;
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    output[0:3] out;
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    input clk;
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    input clk;
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    reg[0:3] value;
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    reg[0:3] value;
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    // Only change the value stored in this
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    // register when the input changes.
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    always @(in) begin
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    always @(in) begin
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        value = in;
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        value = in;
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    end
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    end
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    assign out = value;
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    assign out = value;
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endmodule
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endmodule
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// This stores the 8-bit product of the multiplication unit. It gets reset
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// when it's right 4 bits change.
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//
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// It will write the value coming in on it's left4 input every negative edge
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// of the clock, only if it is getting the write signal from the control unit.
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// It will then shift the value if it is getting the shift operation from the
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// control unit. Since we NEVER write without a shift, this implementation is
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// safe.
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module MUL4_PRODUCT (left4, right4, shift_op, write_op, out, clk);
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module MUL4_PRODUCT (left4, right4, shift_op, write_op, out, clk);
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    input[0:3] left4, right4;
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    input[0:3] left4, right4;
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    input shift_op, write_op, clk;
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    input shift_op, write_op, clk;
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    output[0:7] out;
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    output[0:7] out;
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    // Storage register
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    reg[0:7] value;
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    reg[0:7] value;
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    // Reset the storage register whenever the leftmost multiplying number
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    // changes.
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    always @(right4) begin
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    always @(right4) begin
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        value[0:3] = 'b0000;
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        value[0:3] = 'b0000;
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        value[4:7] = right4;
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        value[4:7] = right4;
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    end
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    end
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    // Every time we get to the negative edge of the clock, we should check
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    // and see if we need to WRITE + SHIFT, or just SHIFT, based on the
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    // signals sent from the control unit.
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    always @(negedge clk) begin
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    always @(negedge clk) begin
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        if (shift_op == 1) begin
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        if (shift_op == 1) begin
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            if (write_op == 1) begin
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            if (write_op == 1) begin
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                // Write the ALU's value into the left half of the register.
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                value[0:3] = left4[0:3];
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                value[0:3] = left4[0:3];
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            end
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            end
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            // Shift the register, since we got a shift signal. This is here
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            // to make sure that we write FIRST, then shift SECOND.
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            value = value >> 1;
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            value = value >> 1;
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        end
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        end
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    end
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    end
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    // Set the output to the new value in the storage register.
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    assign out = value;
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    assign out = value;
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endmodule
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endmodule
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module testme;
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    reg[0:3] a, b;
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    wire[0:7] w_out;
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    MUL4 mult (a, b, w_out);
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    initial begin
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        $monitor ("time=%0d a=%b b=%b prod=%b", $time, a, b, w_out);
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// The actual multiplier unit. It takes 10 "$time" units from when you give
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    end
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    initial begin
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            a = 'b0011; b = 'b0011;
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        #10 a = 'b0001; b = 'b1100;
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        #10 a = 'b1100; b = 'b0011;
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// the inputs until the output is set correctly.
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        #10 a = 'b0101; b = 'b1010;
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        #8
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        #2 $finish;
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    end
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endmodule
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module MUL4 (a, b, out);
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module MUL4 (a, b, out);
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    input[0:3] a, b;
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    input[0:3] a, b;
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    output[0:7] out;
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    output[0:7] out;
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    reg[0:3] counter;
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    reg[0:3] counter;
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    reg clk;
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    reg clk;
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    // Set initial variable values
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    initial begin
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    initial begin
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        clk = 'b0;
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        clk = 'b0;
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        counter ='b0000;
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        counter ='b0000;
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        cin = 'b0;
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        cin = 'b0;
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    end
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    end
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    // Clock generator
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    always begin
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    always begin
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        #1 clk = ~clk;
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        #1 clk = ~clk;
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    end
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    end
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    // Increment the counter at the negative edge of the clock
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    always @(negedge clk) begin
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    always @(negedge clk) begin
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        counter = counter + 'b1;
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        counter = counter + 'b1;
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    end
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    end
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    /* //DEBUGGING INFORMATION
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    /* //DEBUGGING INFORMATION
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    initial begin
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    initial begin
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        $monitor ("time=%0d counter=%b clk=%b w_mout=%b w_prod=%b w_aop=%b w_sop=%b w_wop=%b out=%b",
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        $monitor ("time=%0d counter=%b clk=%b w_mout=%b w_prod=%b w_aop=%b w_sop=%b w_wop=%b out=%b",
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               $time, counter, clk, w_mout, w_prod, w_aop, w_sop, w_wop, out);
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               $time, counter, clk, w_mout, w_prod, w_aop, w_sop, w_wop, out);
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    end
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    end
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    */
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    */
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    wire[0:7] w_prod;
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    wire[0:7] w_prod;
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    wire[0:3] w_mout, w_alu_out;
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    wire[0:3] w_mout, w_alu_out;
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    wire[0:1] w_aop;
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    wire[0:1] w_aop;
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    wire w_sop, w_wop, w_cout;
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    wire w_sop, w_wop, w_cout;
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    reg cin;
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    reg cin;
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    // Also reset the counter every time it reaches 4, it is used
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    // Also reset the counter every time it reaches 4, it is used
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    // to keep the MUL4_CONTROL in sync.
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    // to keep the MUL4_CONTROL in sync.
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    always @(counter) begin
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    always @(counter) begin
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        if (counter == 4) begin
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        if (counter == 4) begin
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            force out = w_prod; // set the output
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            force out = w_prod; // set the output
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            counter = 'b1111; // reset counter
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            counter = 'b1111;   // reset counter
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        end else begin
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        end else begin
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            release out;
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            release out;
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        end
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        end
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    end
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    end
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