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//module a 1-bit adder
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//module a 1-bit adder
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module OneBitAdder (carryIn, a, b, carryOut, sum);
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module OneBitAdder (carryIn, a, b, carryOut, sum);
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   input carryIn, a, b;
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   input carryIn, a, b;
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   output carryOut, sum;
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   output carryOut, sum;
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   Sum sum (carryIn, a, b, sum);
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   Sum sum_gate (carryIn, a, b, sum);
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   CarryOut cout (carryIn, a, b, carryOut);
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   CarryOut cout (carryIn, a, b, carryOut);
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endmodule
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endmodule
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// module for the 1-bit ALU
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// module for the 1-bit ALU
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   OneBitAdder adder (carryIn, a, w2, carryOut, w5);
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   OneBitAdder adder (carryIn, a, w2, carryOut, w5);
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   Mux4 mux4 (w3, w4, w5, dead, op, result);
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   Mux4 mux4 (w3, w4, w5, dead, op, result);
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endmodule
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endmodule
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//Test bench for 1-bit ALU
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module ALU1test;
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        reg a, b, binv, cin;
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        reg [0:1]op;
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        wire cout, result;
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initial begin
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    a=0; b=0;binv=0;op=00;cin=0;
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    #1 a=0; b=1;
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    #1 a=1; b=0;
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    #1 a=1; b=1;
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    #1 a=0; b=0; op=01;
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    #1 a=0; b=1;
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    #1 a=1; b=0;
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    #1 a=1; b=1;
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    #1 a=0; b=0; op=10;
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    #1 a=0; b=1;
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    #1 a=1; b=0;
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    #1 a=1; b=1;
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    #1 a=0; b=0; cin=1;
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    #1 a=0; b=1;
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    #1 a=1; b=0;
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    #1 a=1; b=1;
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end
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/*
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initial begin
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module test_alu1;
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   $display( "time     A     B    op     cin   cout result  ");
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   $monitor("time=%0d a=%b  b=%b  op=%b  cin=%b  cout=%b, result=%b",
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              $time, a, b, op, cin, cout, result);
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end
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    reg a, b, cin, binvert;
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    reg[0:1] op;
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    wire cout, result;
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   ALU1 g1(a,b,binv,cin,op,cout,result);
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    ALU1 alu1 (a, b, binvert, cin, op, cout, result);
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    initial begin
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        $monitor ("time=%0d a=%b b=%b op=%b cin=%b cout=%b result=%b",
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            $time, a, b, op, cin, cout, result);
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    end
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    initial begin
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        binvert=0;
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           a=0; b=0; cin=0; op=00; $display; $display("AND");
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        #1 a=0; b=0; cin=1; op=00;
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        #1 a=0; b=1; cin=0; op=00;
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        #1 a=0; b=1; cin=1; op=00;
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        #1 a=1; b=0; cin=0; op=00;
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        #1 a=1; b=0; cin=1; op=00;
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        #1 a=1; b=1; cin=0; op=00;
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        #1 a=1; b=1; cin=1; op=00;
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        #1 a=0; b=0; cin=0; op=01; $display; $display ("OR");
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        #1 a=0; b=0; cin=1; op=01;
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        #1 a=0; b=1; cin=0; op=01;
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        #1 a=0; b=1; cin=1; op=01;
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        #1 a=1; b=0; cin=0; op=01;
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        #1 a=1; b=0; cin=1; op=01;
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        #1 a=1; b=1; cin=0; op=01;
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        #1 a=1; b=1; cin=1; op=01;
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        #1 a=0; b=0; cin=0; op='b10; $display; $display ("ADD");
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        #1 a=0; b=0; cin=1; op='b10;
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        #1 a=0; b=1; cin=0; op='b10;
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        #1 a=0; b=1; cin=1; op='b10;
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        #1 a=1; b=0; cin=0; op='b10;
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        #1 a=1; b=0; cin=1; op='b10;
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        #1 a=1; b=1; cin=0; op='b10;
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        #1 a=1; b=1; cin=1; op='b10; // <-- BUG HERE
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        binvert=1;
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        #1 a=0; b=0; cin=0; op='b10; $display; $display ("SUB");
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        #1 a=0; b=0; cin=1; op='b10;
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        #1 a=0; b=1; cin=0; op='b10;
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        #1 a=0; b=1; cin=1; op='b10;
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        #1 a=1; b=0; cin=0; op='b10;
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        #1 a=1; b=0; cin=1; op='b10;
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        #1 a=1; b=1; cin=0; op='b10;
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        #1 a=1; b=1; cin=1; op='b10;
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    end
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endmodule
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endmodule
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*/
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