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//Basic unit: 2-input and gate
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//Basic unit: 2-input and gate
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module AND_2 (in1, in2, out);
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module AND_2 (in1, in2, out);
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   input in1, in2;
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   input in1, in2;
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   output out;
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   output out;
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   assign out = in1 & in2;
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   assign out = in1 & in2;
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endmodule
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endmodule
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//Basic unit: 2-input or gate
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//Basic unit: 2-input or gate
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module OR_2 (in1, in2, out);
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module OR_2 (in1, in2, out);
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endmodule
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endmodule
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//Basic unit: 3-input and gate
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//Basic unit: 3-input and gate
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module AND_3 (in1, in2, in3, out);
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module AND_3 (in1, in2, in3, out);
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   input in1, in2, in3;
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   input in1, in2, in3;
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   output out;
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   output out;
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   assign out = in1 & in2 & in3;
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   assign out = in1 & in2 & in3;
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endmodule
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endmodule
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//Basic unit: 4-input or gate
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//Basic unit: 4-input or gate
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module OR_4 (in1, in2, in3, in4, out);
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module OR_4 (in1, in2, in3, in4, out);
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   input a, b, op;
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   input a, b, op;
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   output out;
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   output out;
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   wire w1, w2, w3;
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   wire w1, w2, w3;
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   NOT_1 not1 (op, w1);
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   NOT_1 not1 (op, w1);
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   AND_2 and2 (a, w1, w2);
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   AND_2 and2 (a, w1, w2);
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   AND_2 and1 (b, op, w3);
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   AND_2 and1 (b, op, w3);
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   OR_2 or1 (w2, w3, out);
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   OR_2 or1 (w2, w3, out);
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endmodule
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endmodule
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//basic unit: 3-input NAND gate
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//basic unit: 3-input NAND gate
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module NAND_3 (in1, in2, in3, out);
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module NAND_3 (in1, in2, in3, out);
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  input in1, in2, in3;
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  input in1, in2, in3;
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  output out;
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  output out;
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  assign out = ~(in1 & in2 & in3);
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  assign out = ~(in1 & in2 & in3);
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endmodule
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endmodule
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//basic unit: 4-input NAND gate
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//basic unit: 4-input NAND gate
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module NAND_4 (in1, in2, in3, in4, out);
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module NAND_4 (in1, in2, in3, in4, out);
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endmodule
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endmodule
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// basic unit: 2-input NAND gate
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// basic unit: 2-input NAND gate
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module NAND_2 (in1, in2, out);
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module NAND_2 (in1, in2, out);
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   input in1, in2;
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   input in1, in2;
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   output out;
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   output out;
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   assign out = ~(in1 & in2);
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   assign out = ~(in1 & in2);
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endmodule
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endmodule
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// basic unit: 2-input NOR gate
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// basic unit: 2-input NOR gate
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module NOR_2 ( in1, in2, out);
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module NOR_2 ( in1, in2, out);
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   input [0:1]op;
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   input [0:1]op;
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   output out;
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   output out;
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   wire w1, w2, f1, f2, f3, f4;
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   wire w1, w2, f1, f2, f3, f4;
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   //instantiate two NOT gates
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   //instantiate two NOT gates
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   NOT_1 not1 (op[0:0], w1);
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   NOT_1 not1 (op[0:0], w1);
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   NOT_1 not2 (op[1:1], w2);
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   NOT_1 not2 (op[1:1], w2);
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   //instantiate four 3-input NAND gates
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   //instantiate four 3-input NAND gates
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   NAND_3 nand3_1 (a, w1, w2, f1);
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   NAND_3 nand3_1 (a, w1, w2, f1);
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   NAND_3 nand3_2 (b, w1, op[1:1], f2);
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   NAND_3 nand3_2 (b, w1, op[1:1], f2);
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   Sum sum_gate (carryIn, a, b, sum);
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   Sum sum_gate (carryIn, a, b, sum);
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   CarryOut cout (carryIn, a, b, carryOut);
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   CarryOut cout (carryIn, a, b, carryOut);
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endmodule
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endmodule
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// module for the 1-bit ALU
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// module for the 1-bit ALU
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module ALU1 (a, b, binvert, carryIn, op, carryOut, result);
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module ALU1 (a, b, binvert, carryIn, op, carryOut, result);
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   input a, b, binvert, carryIn;
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   input a, b, binvert, carryIn;
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   input [0:1]op;
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   input [0:1]op;
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   output carryOut, result;
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   output carryOut, result;
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   OneBitAdder adder (carryIn, a, w2, carryOut, w5);
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   OneBitAdder adder (carryIn, a, w2, carryOut, w5);
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   Mux4 mux4 (w3, w4, w5, dead, op, result);
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   Mux4 mux4 (w3, w4, w5, dead, op, result);
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endmodule
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endmodule
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/*
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module test_alu1;
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module test_alu1;
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    reg a, b, cin, binvert;
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    reg a, b, cin, binvert;
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    reg[0:1] op;
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    reg[0:1] op;
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    wire cout, result;
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    wire cout, result;
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        #1 a=1; b=1; cin=0; op='b10;
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        #1 a=1; b=1; cin=0; op='b10;
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        #1 a=1; b=1; cin=1; op='b10;
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        #1 a=1; b=1; cin=1; op='b10;
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    end
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    end
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endmodule
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endmodule
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*/
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