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    /* MUX the output together */
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    /* MUX the output together */
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    Mux4 resMux (w_and, w_or, w_add_out, w_add_out, op, result);
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    Mux4 resMux (w_and, w_or, w_add_out, w_add_out, op, result);
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endmodule
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endmodule
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/*
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module test_oba;
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    reg a, b, cin;
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    wire w_cout, w_result;
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    OneBitAdder oba (cin, a, b, w_cout, w_result);
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    initial begin
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        $monitor ("time=%0d a=%b b=%b cin=%b cout=%b result=%b",
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            $time, a, b, cin, w_cout, w_result);
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    end
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    initial begin
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           a=0; b=0; cin=0;
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        #1 a=0; b=0; cin=1;
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        #1 a=0; b=1; cin=0;
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        #1 a=0; b=1; cin=1;
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        #1 a=1; b=0; cin=0;
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        #1 a=1; b=0; cin=1;
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        #1 a=1; b=1; cin=0;
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        #1 a=1; b=1; cin=1;
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    end
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endmodule
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*/
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/*
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module test_alu1;
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    reg a, b, cin;
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    reg[0:1] op;
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    wire cout, result;
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    ALU1 alu1 (a, b, cin, op, cout, result);
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    initial begin
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        $monitor ("time=%0d a=%b b=%b op=%b cin=%b cout=%b result=%b",
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            $time, a, b, op, cin, cout, result);
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    end
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    initial begin
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           a=0; b=0; cin=0; op=00; $display; $display("AND");
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        #1 a=0; b=0; cin=1; op=00;
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        #1 a=0; b=1; cin=0; op=00;
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        #1 a=0; b=1; cin=1; op=00;
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        #1 a=1; b=0; cin=0; op=00;
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        #1 a=1; b=0; cin=1; op=00;
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        #1 a=1; b=1; cin=0; op=00;
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        #1 a=1; b=1; cin=1; op=00;
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        #1 a=0; b=0; cin=0; op=01; $display; $display ("OR");
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        #1 a=0; b=0; cin=1; op=01;
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        #1 a=0; b=1; cin=0; op=01;
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        #1 a=0; b=1; cin=1; op=01;
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        #1 a=1; b=0; cin=0; op=01;
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        #1 a=1; b=0; cin=1; op=01;
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        #1 a=1; b=1; cin=0; op=01;
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        #1 a=1; b=1; cin=1; op=01;
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        #1 a=0; b=0; cin=0; op=10; $display; $display ("ADD");
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        #1 a=0; b=0; cin=1; op=10;
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        #1 a=0; b=1; cin=0; op=10;
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        #1 a=0; b=1; cin=1; op=10;
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        #1 a=1; b=0; cin=0; op=10;
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        #1 a=1; b=0; cin=1; op=10;
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        #1 a=1; b=1; cin=0; op=10;
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        #1 a=1; b=1; cin=1; op=10;
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        #1 a=0; b=0; cin=0; op=11; $display; $display ("SUB");
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        #1 a=0; b=0; cin=1; op=11;
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        #1 a=0; b=1; cin=0; op=11;
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        #1 a=0; b=1; cin=1; op=11;
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        #1 a=1; b=0; cin=0; op=11;
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        #1 a=1; b=0; cin=1; op=11;
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        #1 a=1; b=1; cin=0; op=11;
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        #1 a=1; b=1; cin=1; op=11;
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    end
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endmodule
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*/
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