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//Basic unit: 2-input or gate
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//Basic unit: 2-input or gate
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module OR_2 (in1, in2, out);
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module OR_2 (in1, in2, out);
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   input in1, in2;
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   input in1, in2;
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   output out;
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   output out;
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   assign out = in1 || in2;
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   assign out = in1 | in2;
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endmodule
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endmodule
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//Basic unit: 3-input or gate
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//Basic unit: 3-input or gate
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module OR_3(in1, in2, in3, out);
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module OR_3(in1, in2, in3, out);
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   input in1, in2, in3;
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   input in1, in2, in3;
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   output out;
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   output out;
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   assign out = in1 || in2 || in3;
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   assign out = in1 | in2 | in3;
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endmodule
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endmodule
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//Basic unit: 3-input and gate
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//Basic unit: 3-input and gate
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module AND_3 (in1, in2, in3, out);
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module AND_3 (in1, in2, in3, out);
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   input in1, in2, in3;
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   input in1, in2, in3;
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//Basic unit: 4-input or gate
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//Basic unit: 4-input or gate
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module OR_4 (in1, in2, in3, in4, out);
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module OR_4 (in1, in2, in3, in4, out);
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   input in1, in2, in3, in4;
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   input in1, in2, in3, in4;
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   output out;
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   output out;
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   assign out = in1 || in2 || in3 || in4;
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   assign out = in1 | in2 | in3 | in4;
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endmodule
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endmodule
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//Basic unit: Invert
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//Basic unit: Invert
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module NOT_1 (in, out);
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module NOT_1 (in, out);
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   input in;
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   input in;
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// basic unit: 2-input NOR gate
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// basic unit: 2-input NOR gate
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module NOR_2 ( in1, in2, out);
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module NOR_2 ( in1, in2, out);
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   input in1, in2;
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   input in1, in2;
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   output out;
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   output out;
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   assign out = ~(in1 || in2);
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   assign out = ~(in1 | in2);
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endmodule
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endmodule
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// module for a 4x1 multiplexer
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// module for a 4x1 multiplexer
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module Mux4 (a, b, c, d, op, out);
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module Mux4 (a, b, c, d, op, out);
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   input a, b, c, d;
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   input a, b, c, d;
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   OR_4 or1 (f1, f2, f3, f4, sum);
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   OR_4 or1 (f1, f2, f3, f4, sum);
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endmodule
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endmodule
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//module a 1-bit adder
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//module a 1-bit adder
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module OneBitAdder (carryIn, a, b, carryOut, sum);
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module OneBitAdder (carryIn, a, b, carryOut, result);
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   input carryIn, a, b;
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   input carryIn, a, b;
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   output carryOut, sum;
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   output carryOut, result;
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   Sum sum (carryIn, a, b, sum);
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   Sum sum (carryIn, a, b, result);
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   CarryOut cout (carryIn, a, b, carryOut);
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   CarryOut cout (carryIn, a, b, carryOut);
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endmodule
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endmodule
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// module for the 1-bit ALU
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// module for the 1-bit ALU
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module ALU1 (a, b, cin, op, cout, result);
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module ALU1 (a, b, cin, op, cout, result);
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    input a, b, cin;
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    input a, b, cin;
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    input[0:1] op; /* 00=AND, 01=OR, 10=ADD, 11=SUB */
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    input[0:1] op; /* 00=AND, 01=OR, 10=ADD, 11=ADD A+~B */
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    output cout, result;
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    output cout, result;
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    wire w_or, w_and, w_binv, w_add_out, w_sub_out;
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    wire w_or, w_and, w_binv, w_add_out, w_sub_out;
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    /* AND, OP=00 */
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    /* AND, OP=00 */
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    /* OR, OP=01 */
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    /* OR, OP=01 */
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    AND_2 and1 (a, b, w_and);
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    AND_2 and1 (a, b, w_and);
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    /* ADD, OP=10 */
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    /* ADD, OP=10 */
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    OneBitAdder add (cin, a, b, cout, w_add_out);
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    /* SUB, OP=11 */
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    /* SUB, OP=11 */
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    NOT_1 not1 (b, w_binv);
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    NOT_1 not1 (b, w_binv);
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    Mux2 m_binv (b, w_binv, op[1], w_adder_b);
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    OneBitAdder sub (cin, a, w_binv, cout, w_sub_out);
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    OneBitAdder add (cin, a, w_adder_b, cout, w_add_out);
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    /* MUX the output together */
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    /* MUX the output together */
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    Mux4 resMux (w_and, w_or, w_add_out, w_sub_out, op, result);
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    Mux4 resMux (w_and, w_or, w_add_out, w_add_out, op, result);
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endmodule
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endmodule
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//Test bench for 1-bit ALU
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module ALU1test;
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        reg a, b, cin;
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        reg [0:1]op;
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        wire cout, result;
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/*
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initial begin
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    a=0; b=0;op=00;cin=0;
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    #1 a=0; b=1;
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    #1 a=1; b=0;
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    #1 a=1; b=1;
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    #1 a=0; b=0; op=01;
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    #1 a=0; b=1;
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    #1 a=1; b=0;
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module test_oba;
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    #1 a=1; b=1;
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    #1 a=0; b=0; op=10;
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    #1 a=0; b=1;
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    #1 a=1; b=0;
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    #1 a=1; b=1;
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    #1 a=0; b=0; cin=1;
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    #1 a=0; b=1;
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    #1 a=1; b=0;
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    #1 a=1; b=1;
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end
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initial begin
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   $display( "time     A     B    op     cin   cout result  ");
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   $monitor("time=%0d a=%b  b=%b  op=%b  cin=%b  cout=%b, result=%b",
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              $time, a, b, op, cin, cout, result);
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end
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    reg a, b, cin;
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    wire w_cout, w_result;
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    OneBitAdder oba (cin, a, b, w_cout, w_result);
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    initial begin
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        $monitor ("time=%0d a=%b b=%b cin=%b cout=%b result=%b",
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            $time, a, b, cin, w_cout, w_result);
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    end
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    initial begin
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           a=0; b=0; cin=0;
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        #1 a=0; b=0; cin=1;
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        #1 a=0; b=1; cin=0;
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        #1 a=0; b=1; cin=1;
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        #1 a=1; b=0; cin=0;
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        #1 a=1; b=0; cin=1;
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        #1 a=1; b=1; cin=0;
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        #1 a=1; b=1; cin=1;
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    end
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endmodule
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*/
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/*
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module test_alu1;
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    reg a, b, cin;
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    reg[0:1] op;
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    wire cout, result;
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208 
   ALU1 g1(a,b,cin,op,cout,result);
 209 
    ALU1 alu1 (a, b, cin, op, cout, result);
- 
 
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    initial begin
- 
 
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        $monitor ("time=%0d a=%b b=%b op=%b cin=%b cout=%b result=%b",
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            $time, a, b, op, cin, cout, result);
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    end
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    initial begin
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           a=0; b=0; cin=0; op=00; $display; $display("AND");
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        #1 a=0; b=0; cin=1; op=00;
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        #1 a=0; b=1; cin=0; op=00;
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        #1 a=0; b=1; cin=1; op=00;
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        #1 a=1; b=0; cin=0; op=00;
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        #1 a=1; b=0; cin=1; op=00;
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        #1 a=1; b=1; cin=0; op=00;
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        #1 a=1; b=1; cin=1; op=00;
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        #1 a=0; b=0; cin=0; op=01; $display; $display ("OR");
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        #1 a=0; b=0; cin=1; op=01;
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        #1 a=0; b=1; cin=0; op=01;
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        #1 a=0; b=1; cin=1; op=01;
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        #1 a=1; b=0; cin=0; op=01;
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        #1 a=1; b=0; cin=1; op=01;
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        #1 a=1; b=1; cin=0; op=01;
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        #1 a=1; b=1; cin=1; op=01;
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        #1 a=0; b=0; cin=0; op=10; $display; $display ("ADD");
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        #1 a=0; b=0; cin=1; op=10;
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        #1 a=0; b=1; cin=0; op=10;
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        #1 a=0; b=1; cin=1; op=10;
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        #1 a=1; b=0; cin=0; op=10;
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        #1 a=1; b=0; cin=1; op=10;
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        #1 a=1; b=1; cin=0; op=10;
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        #1 a=1; b=1; cin=1; op=10;
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        #1 a=0; b=0; cin=0; op=11; $display; $display ("SUB");
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        #1 a=0; b=0; cin=1; op=11;
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        #1 a=0; b=1; cin=0; op=11;
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        #1 a=0; b=1; cin=1; op=11;
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        #1 a=1; b=0; cin=0; op=11;
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        #1 a=1; b=0; cin=1; op=11;
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        #1 a=1; b=1; cin=0; op=11;
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        #1 a=1; b=1; cin=1; op=11;
- 
 
 252 
    end
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endmodule
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endmodule
- 
 
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*/