Subversion Repositories programming

Rev

Rev 192 | Rev 195 | Go to most recent revision | Show entire file | Ignore whitespace | Details | Blame | Last modification | View Log | RSS feed

Rev 192 Rev 194
Line 1... Line 1...
1 
 
 1 
 
2 
//Basic unit: 2-input and gate
 2 
//Basic unit: 2-input and gate
3 
module AND_2 (in1, in2, out);
 3 
module AND_2 (in1, in2, out);
4 
   input in1, in2;
 4 
   input in1, in2;
5 
   output out;
5 
   output out;
6 
   assign out = in1 & in2;
 6 
   assign out = in1 & in2;
7 
endmodule
 7 
endmodule
8 
 
 8 
 
9 
//Basic unit: 2-input or gate
 9 
//Basic unit: 2-input or gate
10 
module OR_2 (in1, in2, out);
 10 
module OR_2 (in1, in2, out);
Line 21... Line 21...
21 
endmodule
 21 
endmodule
22 
 
 22 
 
23 
//Basic unit: 3-input and gate
 23 
//Basic unit: 3-input and gate
24 
module AND_3 (in1, in2, in3, out);
 24 
module AND_3 (in1, in2, in3, out);
25 
   input in1, in2, in3;
 25 
   input in1, in2, in3;
26 
   output out;
26 
   output out;
27 
   assign out = in1 & in2 & in3;
 27 
   assign out = in1 & in2 & in3;
28 
endmodule
 28 
endmodule
29 
 
 29 
 
30 
//Basic unit: 4-input or gate
 30 
//Basic unit: 4-input or gate
31 
module OR_4 (in1, in2, in3, in4, out);
 31 
module OR_4 (in1, in2, in3, in4, out);
Line 46... Line 46...
46 
   input a, b, op;
 46 
   input a, b, op;
47 
   output out;
 47 
   output out;
48 
   wire w1, w2, w3;
 48 
   wire w1, w2, w3;
49 
 
 49 
 
50 
   NOT_1 not1 (op, w1);
 50 
   NOT_1 not1 (op, w1);
51
51 
 
52 
   AND_2 and2 (a, w1, w2);
 52 
   AND_2 and2 (a, w1, w2);
53 
   AND_2 and1 (b, op, w3);
 53 
   AND_2 and1 (b, op, w3);
54 
 
 54 
 
55 
   OR_2 or1 (w2, w3, out);
 55 
   OR_2 or1 (w2, w3, out);
56 
endmodule
 56 
endmodule
57 
 
 57 
 
58 
//basic unit: 3-input NAND gate
 58 
//basic unit: 3-input NAND gate
59 
module NAND_3 (in1, in2, in3, out);
 59 
module NAND_3 (in1, in2, in3, out);
60 
  input in1, in2, in3;
 60 
  input in1, in2, in3;
61 
  output out;
61 
  output out;
62 
  assign out = ~(in1 & in2 & in3);
 62 
  assign out = ~(in1 & in2 & in3);
63 
endmodule
 63 
endmodule
64 
 
 64 
 
65 
//basic unit: 4-input NAND gate
 65 
//basic unit: 4-input NAND gate
66 
module NAND_4 (in1, in2, in3, in4, out);
 66 
module NAND_4 (in1, in2, in3, in4, out);
Line 70... Line 70...
70 
endmodule
 70 
endmodule
71 
 
 71 
 
72 
// basic unit: 2-input NAND gate
 72 
// basic unit: 2-input NAND gate
73 
module NAND_2 (in1, in2, out);
 73 
module NAND_2 (in1, in2, out);
74 
   input in1, in2;
 74 
   input in1, in2;
75 
   output out;
75 
   output out;
76 
   assign out = ~(in1 & in2);
 76 
   assign out = ~(in1 & in2);
77 
endmodule
 77 
endmodule
78 
 
 78 
 
79 
// basic unit: 2-input NOR gate
 79 
// basic unit: 2-input NOR gate
80 
module NOR_2 ( in1, in2, out);
 80 
module NOR_2 ( in1, in2, out);
Line 89... Line 89...
89 
   input [0:1]op;
 89 
   input [0:1]op;
90 
   output out;
 90 
   output out;
91 
   wire w1, w2, f1, f2, f3, f4;
 91 
   wire w1, w2, f1, f2, f3, f4;
92 
 
 92 
 
93 
   //instantiate two NOT gates
 93 
   //instantiate two NOT gates
94 
   NOT_1 not1 (op[0:0], w1);
94 
   NOT_1 not1 (op[0:0], w1);
95 
   NOT_1 not2 (op[1:1], w2);
 95 
   NOT_1 not2 (op[1:1], w2);
96 
 
 96 
 
97 
   //instantiate four 3-input NAND gates
 97 
   //instantiate four 3-input NAND gates
98 
   NAND_3 nand3_1 (a, w1, w2, f1);
 98 
   NAND_3 nand3_1 (a, w1, w2, f1);
99 
   NAND_3 nand3_2 (b, w1, op[1:1], f2);
 99 
   NAND_3 nand3_2 (b, w1, op[1:1], f2);
Line 145... Line 145...
145 
 
 145 
 
146 
   Sum sum (carryIn, a, b, sum);
 146 
   Sum sum (carryIn, a, b, sum);
147 
   CarryOut cout (carryIn, a, b, carryOut);
 147 
   CarryOut cout (carryIn, a, b, carryOut);
148 
endmodule
 148 
endmodule
149 
 
 149 
 
150
150 
 
151 
// module for the 1-bit ALU
 151 
// module for the 1-bit ALU
152 
module ALU1 (a, b, binvert, carryIn, op, carryOut, result);
 152 
module ALU1 (a, b, cin, op, cout, result);
153 
   input a, b, binvert, carryIn;
 153 
    input a, b, cin;
154 
   input [0:1]op;
 154 
    input[0:1] op; /* 00=AND, 01=OR, 10=ADD, 11=SUB */
155 
   output carryOut, result;
 155 
    output cout, result;
- 
 
 156 
 
156 
   wire w1, w2, w3, w4, w5, w6;
 157 
    wire w_or, w_and, w_binv, w_add_out, w_sub_out;
157 
   wire dead;
 - 
 
158 
 
 158 
 
159 
   AND_2 and1 (a, w2, w3);
 159 
    /* AND, OP=00 */
160 
   OR_2 or1 (a, w2, w4);
 160 
    OR_2  or1  (a, b, w_or);
161 
 
 161 
 
162 
   NOT_1 not1 (b, w1);
 162 
    /* OR, OP=01 */
163 
   Mux2 mux2 (b, w1, binvert, w2);
 163 
    AND_2 and1 (a, b, w_and);
164 
 
 164 
 
- 
 
 165 
    /* ADD, OP=10 */
165 
   OneBitAdder adder (carryIn, a, w2, carryOut, w5);
 166 
    OneBitAdder add (cin, a, b, cout, w_add_out);
- 
 
 167 
 
- 
 
 168 
    /* SUB, OP=11 */
- 
 
 169 
    NOT_1 not1 (b, w_binv);
- 
 
 170 
    OneBitAdder sub (cin, a, w_binv, cout, w_sub_out);
- 
 
 171 
 
- 
 
 172 
    /* MUX the output together */
- 
 
 173 
    Mux4 resMux (w_and, w_or, w_add_out, w_sub_out, op, result);
166 
 
 174 
 
167 
   Mux4 mux4 (w3, w4, w5, dead, op, result);
 - 
 
168 
endmodule
 175 
endmodule
169 
 
 176 
 
170 
//Test bench for 1-bit ALU
177 
//Test bench for 1-bit ALU
171 
module ALU1test;
178 
module ALU1test;
172 
        reg a, b, binv, cin;
 179 
        reg a, b, cin;
173 
        reg [0:1]op;
 180 
        reg [0:1]op;
174 
        wire cout, result;
181 
        wire cout, result;
175
182 
 
176 
initial begin
 183 
initial begin
177 
    a=0; b=0;binv=0;op=00;cin=0;
 184 
    a=0; b=0;op=00;cin=0;
178 
    #1 a=0; b=1;
 185 
    #1 a=0; b=1;
179 
    #1 a=1; b=0;
 186 
    #1 a=1; b=0;
180 
    #1 a=1; b=1;
 187 
    #1 a=1; b=1;
181 
    #1 a=0; b=0; op=01;
 188 
    #1 a=0; b=0; op=01;
182 
    #1 a=0; b=1;
189 
    #1 a=0; b=1;
183 
    #1 a=1; b=0;
 190 
    #1 a=1; b=0;
184 
    #1 a=1; b=1;
 191 
    #1 a=1; b=1;
185 
    #1 a=0; b=0; op=10;
 192 
    #1 a=0; b=0; op=10;
186 
    #1 a=0; b=1;
193 
    #1 a=0; b=1;
187 
    #1 a=1; b=0;
194 
    #1 a=1; b=0;
188 
    #1 a=1; b=1;
195 
    #1 a=1; b=1;
189 
    #1 a=0; b=0; cin=1;
 196 
    #1 a=0; b=0; cin=1;
190 
    #1 a=0; b=1;
 197 
    #1 a=0; b=1;
191 
    #1 a=1; b=0;
 198 
    #1 a=1; b=0;
192 
    #1 a=1; b=1;
 199 
    #1 a=1; b=1;
193 
end
 200 
end
194 
 
 201 
 
195 
initial begin
 202 
initial begin
196 
   $display( "time     A     B    op     cin   cout result  ");
 203 
   $display( "time     A     B    op     cin   cout result  ");
197 
   $monitor("time=%0d a=%b  b=%b  op=%b  cin=%b  cout=%b, result=%b",
204 
   $monitor("time=%0d a=%b  b=%b  op=%b  cin=%b  cout=%b, result=%b",
198 
              $time, a, b, op, cin, cout, result);
205 
              $time, a, b, op, cin, cout, result);
199 
end
 206 
end
200 
 
 207 
 
201 
   ALU1 g1(a,b,binv,cin,op,cout,result);
 208 
   ALU1 g1(a,b,cin,op,cout,result);
202 
 
 209 
 
203 
endmodule
 - 
 
204 

            210
            
endmodule

          

          

            -
            
 

            211