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207 ira 1 
/**
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 * Copyright 2006, Ira W. Snyder (devel@irasnyder.com)
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 * License: GNU General Public License v2 (or, at your option, any later
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 * version)
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 */
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/**
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 * Name: Ira Snyder
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 * Class: CS365 - Computer Architecture
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 * Project #1 - Part 2
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 * Due: 2006-02-06
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 */
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/**
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 * File: MUL4_test.v
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 * Purpose: Test module for the MUL4 module.
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 */
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module MUL4_test;
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    reg[0:3] a, b;
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    wire[0:7] w_out;
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    MUL4 mult (a, b, w_out);
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    initial begin
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        $monitor ("time=%0d a=%b b=%b prod=%b", $time, a, b, w_out);
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    end
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    initial begin
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            a = 'b0010; b = 'b1011;
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        #10 a = 'b1010; b = 'b0101;
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        #10 a = 'b1100; b = 'b0011;
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        #10 a = 'b1001; b = 'b0110;
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        #10 $finish;
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    end
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endmodule
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