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198 ira 1 
/* A 4-bit multiplier, following the algorithm from
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 * Pg. 179, Figure 3.7. */
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module MUL4 (mul1, mul2, result);
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    input[0:3] mul1, mul2;
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    output[0:7] result;
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    wire[0:3] w_alu_out;
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    wire[0:3] w_multiplicand;
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    wire[0:7] w_product;
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    wire[0:1] w_alu_op;
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    wire w_write_op, w_shift_op;
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    reg clk;
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    reg[0:3] ctr;
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    initial begin
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        clk = 'b0;
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        ctr = 'b0000;
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    end
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    MUL4_MULTIPLICAND m_mcand (mul1, w_multiplicand, clk);
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    MUL4_PRODUCT m_prod (w_alu_out, mul2, w_shift_op, w_write_op, w_product, clk);
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    MUL4_CONTROL m_ctrl (w_product[7], w_alu_op, w_write_op, w_shift_op, clk);
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    ALU4 m_alu (w_product[0:3], w_multiplicand, cin, w_alu_op, cout, w_alu_out);
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    always @(mul1 or mul2) begin
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        repeat (4) begin
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            $display ("clocked");
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            clk = ~clk;
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            ctr = ctr + 1;
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        end
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    end
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endmodule
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module MUL4_CONTROL (prod_in, alu_op, write_op, shift_op, clk);
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    input prod_in, clk;
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    output[0:1] alu_op;
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    output write_op, shift_op;
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    reg[0:1] a_op;
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    reg w_op, s_op;
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    initial begin
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        a_op = 'b00;
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        w_op = 'b0;
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        s_op = 'b0;
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    end
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    always @(clk) begin
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        if (prod_in == 'b1)
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            begin
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                a_op = 'b10; // ADD
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                w_op = 'b1;  // STORE
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                s_op = 'b1;  // SHIFT
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            end
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        else
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            begin
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                a_op = 'b00; // AND, unnecessary
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                w_op = 'b0;  // DO NOT WRITE
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                s_op = 'b1;  // SHIFT
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            end
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    end //always
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    assign alu_op = a_op;
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    assign write_op = w_op;
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    assign shift_op = s_op;
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endmodule
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module MUL4_MULTIPLICAND (in, out, clk);
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    input[0:3] in;
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    output[0:3] out;
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    input clk;
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    reg[0:3] value;
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    always @(in) begin
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        $display ("multiplicand changed");
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        value = in;
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    end
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    assign out = value;
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endmodule
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module MUL4_PRODUCT (left4, right4, shift_op, write_op, out, clk);
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    input[0:3] left4, right4;
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    input shift_op, write_op, clk;
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    output[0:7] out;
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    reg[0:7] value;
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    always @(right4) begin
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        value[0:3] = 'b0000;
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        value[4:7] = right4;
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        $display ("right4 changed");
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    end
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    always @(/*shift_op or write_op or*/ clk) begin
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        $display ("value=%b", value);
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        if (shift_op == 1) begin
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            $display ("shift 1");
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            if (write_op == 1) begin
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                $display ("write 1");
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                value[0:3] = left4[0:3];
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            end
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            value = value >> 1;
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        end
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    end
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    assign out = value;
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endmodule
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module testme;
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    reg[0:3] a, b;
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    wire[0:7] prod;
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    initial begin
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        $monitor ("time=%0d a=%b b=%b prod=%b", $time, a, b, prod);
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    end
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    initial begin
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           a = 'b0000; b = 'b0000;
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        #1 a = 'b0011; b = 'b1111;
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    end
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    MUL4 m4 (a, b, prod);
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endmodule
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