207 |
ira |
1 |
/**
|
|
|
2 |
* Copyright 2006, Ira W. Snyder (devel@irasnyder.com)
|
|
|
3 |
* License: GNU General Public License v2 (or, at your option, any later
|
|
|
4 |
* version)
|
|
|
5 |
*/
|
|
|
6 |
|
|
|
7 |
/**
|
|
|
8 |
* Name: Ira Snyder
|
|
|
9 |
* Class: CS365 - Computer Architecture
|
|
|
10 |
* Project #1 - Part 1
|
|
|
11 |
* Due: 2006-02-06
|
|
|
12 |
*/
|
|
|
13 |
|
|
|
14 |
/**
|
|
|
15 |
* File: ALU4_test.v
|
|
|
16 |
* Purpose: Test the ALU4 module.
|
|
|
17 |
*/
|
|
|
18 |
|
|
|
19 |
module ALU4_test;
|
|
|
20 |
|
|
|
21 |
reg[0:3] a, b;
|
|
|
22 |
reg[0:1] op;
|
|
|
23 |
reg cin;
|
|
|
24 |
wire[0:3] result;
|
|
|
25 |
wire cout;
|
|
|
26 |
|
|
|
27 |
ALU4 alu (a, b, cin, op, cout, result);
|
|
|
28 |
initial begin
|
|
|
29 |
$monitor ("time=%0d a=%b b=%b op=%b cin=%b cout=%b result=%b",
|
|
|
30 |
$time, a, b, op, cin, cout, result);
|
|
|
31 |
end
|
|
|
32 |
|
|
|
33 |
initial begin
|
208 |
ira |
34 |
$display ("Required Values\n");
|
|
|
35 |
a='b0101; b='b1011; op='b00; cin=0;
|
|
|
36 |
#1 a='b0101; b='b1011; op='b01;
|
|
|
37 |
#1 a='b0101; b='b1011; op='b10;
|
|
|
38 |
#1 a='b1101; b='b0011; op='b00;
|
|
|
39 |
#1 a='b1010; b='b0011; op='b01;
|
|
|
40 |
#1 a='b0101; b='b0011; op='b10;
|
|
|
41 |
#1 a='b1010; b='b1001; op='b10;
|
|
|
42 |
|
|
|
43 |
#1 $display ("\n\nMy Own Values\n");
|
|
|
44 |
#1 a='b0000; b='b0000; cin=0; op='b00; $display; $display("AND");
|
207 |
ira |
45 |
#1 a='b0001; b='b0000; cin=0; op='b00;
|
|
|
46 |
#1 a='b0101; b='b1010; cin=0; op='b00;
|
|
|
47 |
#1 a='b1100; b='b1111; cin=0; op='b00;
|
|
|
48 |
#1 a='b1010; b='b1010; cin=0; op='b00;
|
|
|
49 |
|
|
|
50 |
#1 a='b0000; b='b0000; cin=0; op='b01; $display; $display ("OR");
|
|
|
51 |
#1 a='b0001; b='b0000; cin=0; op='b01;
|
|
|
52 |
#1 a='b0101; b='b1010; cin=0; op='b01;
|
|
|
53 |
#1 a='b1100; b='b1111; cin=0; op='b01;
|
|
|
54 |
#1 a='b1010; b='b1010; cin=0; op='b01;
|
|
|
55 |
|
|
|
56 |
#1 a='b0000; b='b0000; cin=0; op='b10; $display; $display ("ADD");
|
|
|
57 |
#1 a='b0001; b='b0000; cin=0; op='b10;
|
|
|
58 |
#1 a='b0001; b='b0000; cin=1; op='b10;
|
|
|
59 |
#1 a='b0001; b='b0001; cin=0; op='b10;
|
|
|
60 |
#1 a='b0001; b='b0001; cin=1; op='b10;
|
|
|
61 |
#1 a='b0011; b='b1100; cin=0; op='b10;
|
|
|
62 |
#1 a='b0011; b='b1100; cin=1; op='b10;
|
|
|
63 |
|
|
|
64 |
#1 a='b0000; b='b0000; cin=0; op='b11; $display; $display ("SUB");
|
|
|
65 |
#1 a='b0001; b='b0001; cin=0; op='b11;
|
|
|
66 |
#1 a='b0001; b='b0001; cin=1; op='b11;
|
|
|
67 |
#1 a='b0011; b='b0001; cin=0; op='b11;
|
|
|
68 |
#1 a='b0011; b='b0001; cin=1; op='b11;
|
|
|
69 |
#1 a='b1001; b='b0001; cin=0; op='b11;
|
|
|
70 |
#1 a='b1001; b='b0001; cin=1; op='b11;
|
|
|
71 |
end
|
|
|
72 |
|
|
|
73 |
endmodule
|
|
|
74 |
|