| 195 |
ira |
1 |
module ALU4 (a, b, cin, op, cout, result);
|
|
|
2 |
input[0:3] a, b;
|
|
|
3 |
input[0:1] op;
|
|
|
4 |
input cin;
|
|
|
5 |
|
|
|
6 |
output[0:3] result;
|
|
|
7 |
output cout;
|
|
|
8 |
|
|
|
9 |
wire bit3_cout, bit2_cout, bit1_cout;
|
|
|
10 |
|
|
|
11 |
ALU1 bit3 (a[3], b[3], cin, op, bit3_cout, result[3]);
|
|
|
12 |
ALU1 bit2 (a[2], b[2], bit3_cout, op, bit2_cout, result[2]);
|
|
|
13 |
ALU1 bit1 (a[1], b[1], bit2_cout, op, bit1_cout, result[1]);
|
|
|
14 |
ALU1 bit0 (a[0], b[0], bit1_cout, op, cout, result[0]);
|
|
|
15 |
endmodule
|
|
|
16 |
|
|
|
17 |
module test_ALU4;
|
|
|
18 |
reg[0:3] x;
|
|
|
19 |
reg[0:3] y;
|
|
|
20 |
reg[0:1] op;
|
|
|
21 |
reg cin;
|
|
|
22 |
|
|
|
23 |
wire[0:3] result;
|
|
|
24 |
wire cout;
|
|
|
25 |
|
|
|
26 |
initial begin
|
|
|
27 |
$monitor ("time=%0d a=%b b=%b op=%b cin=%b cout=%b result=%b",
|
|
|
28 |
$time, x, y, op, cin, cout, result);
|
|
|
29 |
end
|
|
|
30 |
|
|
|
31 |
initial begin
|
|
|
32 |
|
|
|
33 |
x='b0000; y='b0000; op='b00; cin=0; $display ("\nAND");
|
|
|
34 |
#1 x='b0001; y='b0000; op='b00; cin=0;
|
|
|
35 |
#1 x='b0010; y='b0000; op='b00; cin=0;
|
|
|
36 |
#1 x='b0011; y='b0000; op='b00; cin=0;
|
|
|
37 |
#1 x='b0011; y='b1100; op='b00; cin=0;
|
|
|
38 |
#1 x='b1010; y='b0101; op='b00; cin=0;
|
|
|
39 |
#1 x='b1010; y='b1010; op='b00; cin=0;
|
|
|
40 |
#1 x='b0101; y='b0101; op='b00; cin=0;
|
|
|
41 |
|
|
|
42 |
#1 x='b0001; y='b0000; op='b01; cin=0; $display ("\nOR");
|
|
|
43 |
#1 x='b1001; y='b0110; op='b01; cin=0;
|
|
|
44 |
|
|
|
45 |
#1 x='b0001; y='b0001; op='b10; cin=0; $display ("\nADD");
|
|
|
46 |
#1 x='b0011; y='b0011; op='b10; cin=0;
|
|
|
47 |
|
|
|
48 |
#1 x='b0011; y='b0001; op='b11; cin=0; $display ("\nSUB");
|
|
|
49 |
end
|
|
|
50 |
|
|
|
51 |
ALU4 alu4 (x, y, cin, op, cout, result);
|
|
|
52 |
|
|
|
53 |
endmodule
|