Subversion Repositories programming

Rev

Rev 197 | Details | Compare with Previous | Last modification | View Log | RSS feed

Rev Author Line No. Line
207 ira 1 
/**
2 
 * Copyright 2006, Ira W. Snyder (devel@irasnyder.com)
3 
 * License: GNU General Public License v2 (or, at your option, any later
4 
 * version)
5 
 */
197 ira 6 
 
207 ira 7 
/**
8 
 * Name: Ira Snyder
9 
 * Class: CS365 - Computer Architecture
10 
 * Project #1 - Part 1 (support)
11 
 * Due: 2006-02-06
12 
 */
13 
 
14 
/**
15 
 * File: ALU1_test.v
16 
 * Purpose: Test module for the ALU1 module.
17 
 */
18 
 
19 
module ALU1_test;
20 
 
197 ira 21 
    reg a, b, cin;
22 
    reg[0:1] op;
23 
    wire cout, result;
24 
 
25 
    ALU1 alu1 (a, b, cin, op, cout, result);
26 
 
27 
    initial begin
28 
        $monitor ("time=%0d a=%b b=%b op=%b cin=%b cout=%b result=%b",
29 
            $time, a, b, op, cin, cout, result);
30 
    end
31 
 
32 
    initial begin
33 
           a=0; b=0; cin=0; op=00; $display; $display("AND");
34 
        #1 a=0; b=0; cin=1; op=00;
35 
        #1 a=0; b=1; cin=0; op=00;
36 
        #1 a=0; b=1; cin=1; op=00;
37 
        #1 a=1; b=0; cin=0; op=00;
38 
        #1 a=1; b=0; cin=1; op=00;
39 
        #1 a=1; b=1; cin=0; op=00;
40 
        #1 a=1; b=1; cin=1; op=00;
41 
 
42 
        #1 a=0; b=0; cin=0; op=01; $display; $display ("OR");
43 
        #1 a=0; b=0; cin=1; op=01;
44 
        #1 a=0; b=1; cin=0; op=01;
45 
        #1 a=0; b=1; cin=1; op=01;
46 
        #1 a=1; b=0; cin=0; op=01;
47 
        #1 a=1; b=0; cin=1; op=01;
48 
        #1 a=1; b=1; cin=0; op=01;
49 
        #1 a=1; b=1; cin=1; op=01;
50 
 
51 
        #1 a=0; b=0; cin=0; op=10; $display; $display ("ADD");
52 
        #1 a=0; b=0; cin=1; op=10;
53 
        #1 a=0; b=1; cin=0; op=10;
54 
        #1 a=0; b=1; cin=1; op=10;
55 
        #1 a=1; b=0; cin=0; op=10;
56 
        #1 a=1; b=0; cin=1; op=10;
57 
        #1 a=1; b=1; cin=0; op=10;
58 
        #1 a=1; b=1; cin=1; op=10;
59 
 
60 
        #1 a=0; b=0; cin=0; op=11; $display; $display ("SUB");
61 
        #1 a=0; b=0; cin=1; op=11;
62 
        #1 a=0; b=1; cin=0; op=11;
63 
        #1 a=0; b=1; cin=1; op=11;
64 
        #1 a=1; b=0; cin=0; op=11;
65 
        #1 a=1; b=0; cin=1; op=11;
66 
        #1 a=1; b=1; cin=0; op=11;
67 
        #1 a=1; b=1; cin=1; op=11;
68 
    end
69 
 
70 
endmodule
71