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194 ira 1 
 
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//Basic unit: 2-input and gate
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module AND_2 (in1, in2, out);
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   input in1, in2;
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   output out;
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   assign out = in1 & in2;
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endmodule
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//Basic unit: 2-input or gate
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module OR_2 (in1, in2, out);
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   input in1, in2;
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   output out;
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   assign out = in1 || in2;
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endmodule
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//Basic unit: 3-input or gate
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module OR_3(in1, in2, in3, out);
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   input in1, in2, in3;
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   output out;
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   assign out = in1 || in2 || in3;
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endmodule
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//Basic unit: 3-input and gate
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module AND_3 (in1, in2, in3, out);
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   input in1, in2, in3;
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   output out;
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   assign out = in1 & in2 & in3;
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endmodule
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//Basic unit: 4-input or gate
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module OR_4 (in1, in2, in3, in4, out);
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   input in1, in2, in3, in4;
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   output out;
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   assign out = in1 || in2 || in3 || in4;
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endmodule
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//Basic unit: Invert
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module NOT_1 (in, out);
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   input in;
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   output out;
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   assign out = ~in;
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endmodule
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//Basic unit: module for a 2x1 multiplexer
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module Mux2 (a, b, op, out);
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   input a, b, op;
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   output out;
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   wire w1, w2, w3;
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   NOT_1 not1 (op, w1);
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   AND_2 and2 (a, w1, w2);
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   AND_2 and1 (b, op, w3);
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   OR_2 or1 (w2, w3, out);
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endmodule
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//basic unit: 3-input NAND gate
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module NAND_3 (in1, in2, in3, out);
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  input in1, in2, in3;
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  output out;
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  assign out = ~(in1 & in2 & in3);
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endmodule
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//basic unit: 4-input NAND gate
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module NAND_4 (in1, in2, in3, in4, out);
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  input in1, in2, in3, in4;
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  output out;
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  assign out = ~(in1 & in2 & in3 & in4);
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endmodule
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// basic unit: 2-input NAND gate
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module NAND_2 (in1, in2, out);
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   input in1, in2;
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   output out;
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   assign out = ~(in1 & in2);
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endmodule
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// basic unit: 2-input NOR gate
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module NOR_2 ( in1, in2, out);
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   input in1, in2;
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   output out;
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   assign out = ~(in1 || in2);
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endmodule
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// module for a 4x1 multiplexer
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module Mux4 (a, b, c, d, op, out);
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   input a, b, c, d;
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   input [0:1]op;
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   output out;
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   wire w1, w2, f1, f2, f3, f4;
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   //instantiate two NOT gates
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   NOT_1 not1 (op[0:0], w1);
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   NOT_1 not2 (op[1:1], w2);
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   //instantiate four 3-input NAND gates
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   NAND_3 nand3_1 (a, w1, w2, f1);
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   NAND_3 nand3_2 (b, w1, op[1:1], f2);
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   NAND_3 nand3_3 (c, op[0:0], w2, f3);
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   NAND_3 nand3_4 (d, op[0:0], op[1:1], f4);
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   //instantiate one 4-input NAND gate
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   NAND_4 nand4_1 (f1, f2, f3, f4, out);
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endmodule
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// CarryOut module for the 1-bit Adder
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//cout = cin . a + cin . b + a . b
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module CarryOut (carryIn, a, b, carryOut);
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   input carryIn, a, b;
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   output carryOut;
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   wire w1, w2, w3;
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   AND_2  and1 (carryIn, a, w1);
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   AND_2  and2 (carryIn, b, w2);
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   AND_2  and3 (a, b, w3);
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   OR_3   or1 (w1, w2, w3, carryOut);
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endmodule
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//Sum module for 1-bit ALU
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module Sum (carryIn, a, b, sum);
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   input a, b, carryIn;
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   wire w1, w2, w3, f1, f2, f3, f4;
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   output sum;
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   NOT_1 not1 (carryIn, w1);
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   NOT_1 not2 (a, w2);
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   NOT_1 not3 (b, w3);
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   AND_3 and1 (a, w3, w1, f1);
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   AND_3 and2 (w2, b, w1, f2);
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   AND_3 and3 (w2, w3, carryIn, f3);
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   AND_3 and4 (a, b, carryIn, f4);
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   OR_4 or1 (f1, f2, f3, f4, sum);
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endmodule
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//module a 1-bit adder
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module OneBitAdder (carryIn, a, b, carryOut, sum);
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   input carryIn, a, b;
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   output carryOut, sum;
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   Sum sum (carryIn, a, b, sum);
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   CarryOut cout (carryIn, a, b, carryOut);
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endmodule
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// module for the 1-bit ALU
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module ALU1 (a, b, binvert, carryIn, op, carryOut, result);
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   input a, b, binvert, carryIn;
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   input [0:1]op;
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   output carryOut, result;
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   wire w1, w2, w3, w4, w5, w6;
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   wire dead;
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   AND_2 and1 (a, w2, w3);
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   OR_2 or1 (a, w2, w4);
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   NOT_1 not1 (b, w1);
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   Mux2 mux2 (b, w1, binvert, w2);
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   OneBitAdder adder (carryIn, a, w2, carryOut, w5);
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   Mux4 mux4 (w3, w4, w5, dead, op, result);
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endmodule
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//Test bench for 1-bit ALU
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module ALU1test;
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        reg a, b, binv, cin;
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        reg [0:1]op;
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        wire cout, result;
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initial begin
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    a=0; b=0;binv=0;op=00;cin=0;
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    #1 a=0; b=1;
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    #1 a=1; b=0;
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    #1 a=1; b=1;
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    #1 a=0; b=0; op=01;
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    #1 a=0; b=1;
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    #1 a=1; b=0;
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    #1 a=1; b=1;
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    #1 a=0; b=0; op=10;
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    #1 a=0; b=1;
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    #1 a=1; b=0;
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    #1 a=1; b=1;
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    #1 a=0; b=0; cin=1;
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    #1 a=0; b=1;
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    #1 a=1; b=0;
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    #1 a=1; b=1;
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end
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initial begin
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   $display( "time     A     B    op     cin   cout result  ");
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   $monitor("time=%0d a=%b  b=%b  op=%b  cin=%b  cout=%b, result=%b",
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              $time, a, b, op, cin, cout, result);
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end
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   ALU1 g1(a,b,binv,cin,op,cout,result);
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endmodule