Subversion Repositories programming

Rev

Rev 203 | Details | Compare with Previous | Last modification | View Log | RSS feed

Rev Author Line No. Line
207 ira 1 
/**
2 
 * Copyright 2006, Ira W. Snyder (devel@irasnyder.com)
3 
 * License: GNU General Public License v2 (or, at your option, any later
4 
 * version)
5 
 */
192 ira 6 
 
207 ira 7 
/**
8 
 * Name: Ira Snyder
9 
 * Class: CS365 - Computer Architecture
10 
 * Project #1 - Part 1 (support)
11 
 * Due: 2006-02-06
12 
 */
192 ira 13 
 
207 ira 14 
/**
15 
 * File: ALU1.v
16 
 * Purpose: Implementation of a 1-bit ALU.
17 
 */
192 ira 18 
 
194 ira 19 
module ALU1 (a, b, cin, op, cout, result);
20 
    input a, b, cin;
195 ira 21 
    input[0:1] op; /* 00=AND, 01=OR, 10=ADD, 11=ADD A+~B */
194 ira 22 
    output cout, result;
192 ira 23 
 
194 ira 24 
    wire w_or, w_and, w_binv, w_add_out, w_sub_out;
192 ira 25 
 
194 ira 26 
    /* AND, OP=00 */
27 
    OR_2  or1  (a, b, w_or);
192 ira 28 
 
194 ira 29 
    /* OR, OP=01 */
30 
    AND_2 and1 (a, b, w_and);
192 ira 31 
 
194 ira 32 
    /* ADD, OP=10 */
33 
    /* SUB, OP=11 */
34 
    NOT_1 not1 (b, w_binv);
195 ira 35 
    Mux2 m_binv (b, w_binv, op[1], w_adder_b);
203 ira 36 
 
195 ira 37 
    OneBitAdder add (cin, a, w_adder_b, cout, w_add_out);
203 ira 38 
 
194 ira 39 
    /* MUX the output together */
195 ira 40 
    Mux4 resMux (w_and, w_or, w_add_out, w_add_out, op, result);
194 ira 41 
 
192 ira 42 
endmodule
43