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192 ira 1 
 
2 
//Basic unit: 2-input and gate
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module AND_2 (in1, in2, out);
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   input in1, in2;
194 ira 5 
   output out;
192 ira 6 
   assign out = in1 & in2;
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endmodule
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//Basic unit: 2-input or gate
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module OR_2 (in1, in2, out);
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   input in1, in2;
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   output out;
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   assign out = in1 || in2;
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endmodule
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//Basic unit: 3-input or gate
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module OR_3(in1, in2, in3, out);
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   input in1, in2, in3;
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   output out;
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   assign out = in1 || in2 || in3;
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endmodule
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//Basic unit: 3-input and gate
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module AND_3 (in1, in2, in3, out);
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   input in1, in2, in3;
194 ira 26 
   output out;
192 ira 27 
   assign out = in1 & in2 & in3;
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endmodule
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//Basic unit: 4-input or gate
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module OR_4 (in1, in2, in3, in4, out);
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   input in1, in2, in3, in4;
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   output out;
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   assign out = in1 || in2 || in3 || in4;
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endmodule
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//Basic unit: Invert
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module NOT_1 (in, out);
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   input in;
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   output out;
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   assign out = ~in;
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endmodule
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//Basic unit: module for a 2x1 multiplexer
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module Mux2 (a, b, op, out);
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   input a, b, op;
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   output out;
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   wire w1, w2, w3;
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   NOT_1 not1 (op, w1);
194 ira 51 
 
192 ira 52 
   AND_2 and2 (a, w1, w2);
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   AND_2 and1 (b, op, w3);
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   OR_2 or1 (w2, w3, out);
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endmodule
57 
 
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//basic unit: 3-input NAND gate
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module NAND_3 (in1, in2, in3, out);
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  input in1, in2, in3;
194 ira 61 
  output out;
192 ira 62 
  assign out = ~(in1 & in2 & in3);
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endmodule
64 
 
65 
//basic unit: 4-input NAND gate
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module NAND_4 (in1, in2, in3, in4, out);
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  input in1, in2, in3, in4;
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  output out;
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  assign out = ~(in1 & in2 & in3 & in4);
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endmodule
71 
 
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// basic unit: 2-input NAND gate
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module NAND_2 (in1, in2, out);
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   input in1, in2;
194 ira 75 
   output out;
192 ira 76 
   assign out = ~(in1 & in2);
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endmodule
78 
 
79 
// basic unit: 2-input NOR gate
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module NOR_2 ( in1, in2, out);
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   input in1, in2;
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   output out;
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   assign out = ~(in1 || in2);
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endmodule
85 
 
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// module for a 4x1 multiplexer
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module Mux4 (a, b, c, d, op, out);
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   input a, b, c, d;
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   input [0:1]op;
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   output out;
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   wire w1, w2, f1, f2, f3, f4;
92 
 
93 
   //instantiate two NOT gates
194 ira 94 
   NOT_1 not1 (op[0:0], w1);
192 ira 95 
   NOT_1 not2 (op[1:1], w2);
96 
 
97 
   //instantiate four 3-input NAND gates
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   NAND_3 nand3_1 (a, w1, w2, f1);
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   NAND_3 nand3_2 (b, w1, op[1:1], f2);
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   NAND_3 nand3_3 (c, op[0:0], w2, f3);
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   NAND_3 nand3_4 (d, op[0:0], op[1:1], f4);
102 
 
103 
   //instantiate one 4-input NAND gate
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   NAND_4 nand4_1 (f1, f2, f3, f4, out);
105 
endmodule
106 
 
107 
// CarryOut module for the 1-bit Adder
108 
//cout = cin . a + cin . b + a . b
109 
module CarryOut (carryIn, a, b, carryOut);
110 
   input carryIn, a, b;
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   output carryOut;
112 
 
113 
   wire w1, w2, w3;
114 
 
115 
   AND_2  and1 (carryIn, a, w1);
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   AND_2  and2 (carryIn, b, w2);
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   AND_2  and3 (a, b, w3);
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   OR_3   or1 (w1, w2, w3, carryOut);
120 
endmodule
121 
 
122 
//Sum module for 1-bit ALU
123 
module Sum (carryIn, a, b, sum);
124 
   input a, b, carryIn;
125 
   wire w1, w2, w3, f1, f2, f3, f4;
126 
   output sum;
127 
 
128 
   NOT_1 not1 (carryIn, w1);
129 
   NOT_1 not2 (a, w2);
130 
   NOT_1 not3 (b, w3);
131 
 
132 
   AND_3 and1 (a, w3, w1, f1);
133 
   AND_3 and2 (w2, b, w1, f2);
134 
   AND_3 and3 (w2, w3, carryIn, f3);
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   AND_3 and4 (a, b, carryIn, f4);
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137 
   OR_4 or1 (f1, f2, f3, f4, sum);
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139 
endmodule
140 
 
141 
//module a 1-bit adder
142 
module OneBitAdder (carryIn, a, b, carryOut, sum);
143 
   input carryIn, a, b;
144 
   output carryOut, sum;
145 
 
146 
   Sum sum (carryIn, a, b, sum);
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   CarryOut cout (carryIn, a, b, carryOut);
148 
endmodule
149 
 
194 ira 150 
 
192 ira 151 
// module for the 1-bit ALU
194 ira 152 
module ALU1 (a, b, cin, op, cout, result);
153 
    input a, b, cin;
154 
    input[0:1] op; /* 00=AND, 01=OR, 10=ADD, 11=SUB */
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    output cout, result;
192 ira 156 
 
194 ira 157 
    wire w_or, w_and, w_binv, w_add_out, w_sub_out;
192 ira 158 
 
194 ira 159 
    /* AND, OP=00 */
160 
    OR_2  or1  (a, b, w_or);
192 ira 161 
 
194 ira 162 
    /* OR, OP=01 */
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    AND_2 and1 (a, b, w_and);
192 ira 164 
 
194 ira 165 
    /* ADD, OP=10 */
166 
    OneBitAdder add (cin, a, b, cout, w_add_out);
167 
 
168 
    /* SUB, OP=11 */
169 
    NOT_1 not1 (b, w_binv);
170 
    OneBitAdder sub (cin, a, w_binv, cout, w_sub_out);
171 
 
172 
    /* MUX the output together */
173 
    Mux4 resMux (w_and, w_or, w_add_out, w_sub_out, op, result);
174 
 
192 ira 175 
endmodule
176 
 
194 ira 177 
//Test bench for 1-bit ALU
178 
module ALU1test;
179 
        reg a, b, cin;
192 ira 180 
        reg [0:1]op;
194 ira 181 
        wire cout, result;
182 
 
192 ira 183 
initial begin
194 ira 184 
    a=0; b=0;op=00;cin=0;
192 ira 185 
    #1 a=0; b=1;
186 
    #1 a=1; b=0;
187 
    #1 a=1; b=1;
188 
    #1 a=0; b=0; op=01;
194 ira 189 
    #1 a=0; b=1;
192 ira 190 
    #1 a=1; b=0;
191 
    #1 a=1; b=1;
192 
    #1 a=0; b=0; op=10;
194 ira 193 
    #1 a=0; b=1;
194 
    #1 a=1; b=0;
195 
    #1 a=1; b=1;
192 ira 196 
    #1 a=0; b=0; cin=1;
197 
    #1 a=0; b=1;
198 
    #1 a=1; b=0;
199 
    #1 a=1; b=1;
200 
end
201 
 
202 
initial begin
203 
   $display( "time     A     B    op     cin   cout result  ");
194 ira 204 
   $monitor("time=%0d a=%b  b=%b  op=%b  cin=%b  cout=%b, result=%b",
205 
              $time, a, b, op, cin, cout, result);
192 ira 206 
end
207 
 
194 ira 208 
   ALU1 g1(a,b,cin,op,cout,result);
192 ira 209 
 
194 ira 210 
endmodule